
5
AT24C02B [Preliminary]
5181B–SEEPR–1/07
Notes:
1. This parameter is characterized and is not 100% tested (T
A
= 25
°
C).
2. This parameter is characterized.
Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see to
Figure 5 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION:
A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see to Figure 6 on page 7).
STOP CONDITION:
A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 6 on page 7).
ACKNOWLEDGE:
All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has
received each word. This happens during the ninth clock cycle.
STANDBY MODE:
The AT24C02B features a low-power standby mode which is
enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion
of any internal operations.
Table 5.
AC Characteristics
Applicable over recommended operating range from T
A
=
40
°
C to +125
°
C, V
CC
= +2.5V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
Symbol
Parameter
AT24C02B
Units
Min
Max
f
SCL
Clock Frequency, SCL
400
kHz
t
LOW
Clock Pulse Width Low
1.2
μ
s
t
HIGH
Clock Pulse Width High
0.6
μ
s
t
I
Noise Suppression Time
(1)
50
ns
t
AA
Clock Low to Data Out Valid
0.1
0.9
μ
s
t
BUF
Time the bus must be free before
a new transmission can start
(2)
1.2
μ
s
t
HD.STA
Start Hold Time
0.6
μ
s
t
SU.STA
Start Set-up Time
0.6
μ
s
t
HD.DAT
Data In Hold Time
0
μ
s
t
SU.DAT
Data In Set-up Time
100
ns
t
R
Inputs Rise Time
(2)
300
ns
t
F
Inputs Fall Time
(2)
300
ns
t
SU.STO
Stop Set-up Time
0.6
μ
s
t
DH
Data Out Hold Time
50
ns
t
WR
Endurance
(2)
Write Cycle Time
5
ms
5.0V, 25
°
C, Page Mode
1M
Write Cycles