
9
AT24C01B [Preliminary]
5156B–
S
EEPR–5/06
Device Addressing
The 1K EEPROM device requires
 a
n 
8
-
b
it device 
a
ddress word following 
a
 st
a
rt condi-
tion to en
ab
le the chip for 
a
 re
a
d or write oper
a
tion (refer to Figure 7).
The device 
a
ddress word consists of 
a
 m
a
nd
a
tory one, zero sequence for the first four
most signific
a
nt 
b
its 
a
s shown. This is common to 
a
ll the EEPROM devices.
The next 
3
b
its 
a
re the A2, A1 
a
nd A0 device 
a
ddress 
b
its for the 1K EEPROM. These 
3
b
its must comp
a
re to their corresponding h
a
rd-wired input pins.
The eighth 
b
it of the device 
a
ddress is the re
a
d/write oper
a
tion select 
b
it. A re
a
d oper
a
-
tion is initi
a
ted if this 
b
it is high 
a
nd 
a
 write oper
a
tion is initi
a
ted if this 
b
it is low.
Upon 
a
 comp
a
re of the device 
a
ddress, the EEPROM will output 
a
 zero. If 
a
 comp
a
re is
not m
a
de, the chip will return to 
a
 st
a
nd
b
y st
a
te.
Write Operations
BYTE WRITE:
 A write oper
a
tion requires 
a
n 
8
-
b
it d
a
t
a
 word 
a
ddress following the
device 
a
ddress word 
a
nd 
a
cknowledgment. Upon receipt of this 
a
ddress, the EEPROM
will 
a
g
a
in respond with 
a
 zero 
a
nd then clock in the first 
8
-
b
it d
a
t
a
 word. Following
receipt of the 
8
-
b
it d
a
t
a
 word, the EEPROM will output 
a
 zero 
a
nd the 
a
ddressing
device, such 
a
s 
a
 microcontroller, must termin
a
te the write sequence with 
a
 stop condi-
tion. At this time the EEPROM enters 
a
n intern
a
lly timed write cycle, t
WR
, to the
nonvol
a
tile memory. All inputs 
a
re dis
ab
led during this write cycle 
a
nd the EEPROM will
not respond until the write is complete (see Figure 
8
 on p
a
ge 11).
PAGE WRITE:
 The 1K EEPROM is c
a
p
ab
le of 
a
n 
8
-
b
yte p
a
ge write.
A p
a
ge write is initi
a
ted the s
a
me 
a
s 
a
b
yte write, 
b
ut the microcontroller does not send
a
 stop condition 
a
fter the first d
a
t
a
 word is clocked in. Inste
a
d, 
a
fter the EEPROM
a
cknowledges receipt of the first d
a
t
a
 word, the microcontroller c
a
n tr
a
nsmit up to seven
d
a
t
a
 words. The EEPROM will respond with 
a
 zero 
a
fter e
a
ch d
a
t
a
 word received. The
microcontroller must termin
a
te the p
a
ge write sequence with 
a
 stop condition (see Fig-
ure 9 on p
a
ge 11).
The d
a
t
a
 word 
a
ddress lower three 
b
its 
a
re intern
a
lly incremented following the receipt
of e
a
ch d
a
t
a
 word. The higher d
a
t
a
 word 
a
ddress 
b
its 
a
re not incremented, ret
a
ining the
memory p
a
ge row loc
a
tion. When the word 
a
ddress, intern
a
lly gener
a
ted, re
a
ches the
p
a
ge 
b
ound
a
ry, the following 
b
yte is pl
a
ced 
a
t the 
b
eginning of the s
a
me p
a
ge. If more
th
a
n eight d
a
t
a
 words 
a
re tr
a
nsmitted to the EEPROM, the d
a
t
a
 word 
a
ddress will “roll
over” 
a
nd previous d
a
t
a
 will 
b
e overwritten.
ACKNOWLEDGE POLLING:
 Once the intern
a
lly timed write cycle h
a
s st
a
rted 
a
nd the
EEPROM inputs 
a
re dis
ab
led, 
a
cknowledge polling c
a
n 
b
e initi
a
ted. This involves send-
ing 
a
 st
a
rt condition followed 
b
y the device 
a
ddress word. The re
a
d/write 
b
it is
represent
a
tive of the oper
a
tion desired. Only if the intern
a
l write cycle h
a
s completed
will the EEPROM respond with 
a
 zero 
a
llowing the re
a
d or write sequence to continue.
Read Operations
Re
a
d oper
a
tions 
a
re initi
a
ted the s
a
me w
a
y 
a
s write oper
a
tions with the exception th
a
t
the re
a
d/write select 
b
it in the device 
a
ddress word is set to one. There 
a
re three re
a
d
oper
a
tions: current 
a
ddress re
a
d, r
a
ndom 
a
ddress re
a
d 
a
nd sequenti
a
l re
a
d.
CURRENT ADDRESS READ:
 The intern
a
l d
a
t
a
 word 
a
ddress counter m
a
int
a
ins the
l
a
st 
a
ddress 
a
ccessed during the l
a
st re
a
d or write oper
a
tion, incremented 
b
y one. This
a
ddress st
a
ys v
a
lid 
b
etween oper
a
tions 
a
s long 
a
s the chip power is m
a
int
a
ined. The
a
ddress “roll over” during re
a
d is from the l
a
st 
b
yte of the l
a
st memory p
a
ge to the first