參數(shù)資料
型號: AT24C01A-10SI-2.5
廠商: ATMEL CORP
元件分類: DRAM
英文描述: 2-Wire Serial EEPROM
中文描述: 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8
封裝: 0.150 INCH, PLASTIC, SOIC-8
文件頁數(shù): 6/24頁
文件大小: 445K
代理商: AT24C01A-10SI-2.5
6
AT24C01A/02/04/08A/16A
0180V–SEEPR–8/05
Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION:
A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 8).
STOP CONDITION:
A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 8).
ACKNOWLEDGE:
All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock cycle.
STANDBY MODE:
The AT24C01A/02/04/08A/16A features a low-power standby mode
which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the
completion of any internal operations.
MEMORY RESET:
After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
1.
Clock up to 9 cycles.
2.
Look for SDA high in each cycle while SCL is high.
3.
Create a start condition.
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