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參數(shù)資料
| 型號： | AT22LV10L-25JC |
| 廠商： | ATMEL CORP |
| 元件分類： | PLD |
| 英文描述： | Low-Voltage UV Erasable Programmable Logic Device |
| 中文描述： | OT PLD, 25 ns, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 507K |
| 代理商： | AT22LV10L-25JC |
AT22LV10(L)
7
Preload of Registered Outputs
The registers in the AT22LV10 and AT22LV10L are pro-
vided with circuitry to allow loading of each register asyn-
chronously with either a high or a low. This feature will
simplify testing since any state can be forced into the regis-
ters to control test sequencing. A V
IH
level on the I/O pin
will force the register high; a V
IL
will force it low, indepen-
dent of the polarity bit (C0) setting. The preload state is
entered by placing an 11.5V to 13V signal on pin 8 on
DIPs, and pin 10 on SMPs. When the clock pin is pulsed
high, the data on the I/O pins is placed into the ten regis-
ters.
Power-Up Reset
The registers in the AT22LV10 and AT22LV10L are
designed to reset during power up. At a point delayed
slightly from VCC crossing 2.5V, all registers will be reset
to the low state. The output state will depend on the polarity
of the output buffer.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1.
The V
CC
rise must be monotonis;
2.
After reset occurs, all input and feedback setup
times must be met before driving the clock pin high,
and
3.
The clock must remain stable during t
PR
.
Note:
Erasure Characteristics
The entire fuse array of an AT22LV10 or AT22LV10L is
erased after exposure to ultraviolet light at a wavelength of
2537 . Complete erasure is assured after a minimum of
20 minutes exposure using 12,000
μ
W/cm
2
intensity lamps
spaced one inch away from the chip. Minimum erase time
for lamps at other intensity ratings can be calculated from
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
the minimum integrated erasure dose of 15 W
sec/cm
2
. To
prevent unintentional erasure, an opaque label is recom-
mended to cover the clear window on any UV erasable
PLD which will be subjected to continuous fluorescent
indoor lighting or sunlight.
Level forced on registered output
pin during preload cycle
Register state after
cycle
V
IH
High
V
IL
Low
Parameter
Description
Min
Typ
Max
Units
t
PR
Power-Up
Reset Time
600
1000
ns
Pin Capacitance
(f = 1 MHz, T = 25°C)
(1)
Typ
Max
Units
Conditions
C
IN
5
8
pF
V
IN
= 0V
C
OUT
6
8
pF
V
OUT
= 0V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT22LV10L-25JI | Low-Voltage UV Erasable Programmable Logic Device |
| AT22LV10L-25PC | Low-Voltage UV Erasable Programmable Logic Device |
| AT22LV10L-25PI | Circular Connector; No. of Contacts:16; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:36; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:36-14 RoHS Compliant: No |
| AT22LV10L-25SC | Circular Connector; No. of Contacts:16; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:36; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No |
| AT22LV10L-25SI | Hook-Up Wire; Conductor Size AWG:26; No. Strands x Strand Size:7 x 34; Jacket Color:Green; Approval Bodies:UL; Approval Categories:UL AWM Style 1213; Passes VW-1 Flame Test; Cable/Wire MIL SPEC:MIL-W-16878/4 Type E RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT22LV10L-25JI | 功能描述:SPLD - 簡單可編程邏輯器件 500 Gate Low V RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| AT22LV10L-25KC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
| AT22LV10L-25KI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
| AT22LV10L-25LC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
| AT22LV10L-25LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
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