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參數(shù)資料
| 型號： | AT17LV65A-10JI |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-SOIC -55 to 125 |
| 中文描述： | 64K X 1 CONFIGURATION MEMORY, PQCC20 |
| 封裝： | PLASTIC, MS-018AA, LCC-20 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 159K |
| 代理商： | AT17LV65A-10JI |
AT17A Series
9
Notes:
1. Preliminary specifications for military operating range only.
2. AC test lead = 50 pf.
3. Float delays are measured with 5 pF AC loads. Transition is measured
±
200 mV from steady-state active levels.
4. During cascade F
MAX
= 8 MHz.
AC Characteristics
V
CC
= 3.3V
±
10%
Symbol
Description
Commercial
Industrial/Military
Units
Min
Max
Min
Max
t
OE
(2)
OE to Data Delay
40
45
ns
t
CE
(2)
CE to Data Delay
60
60
ns
t
CAC
(2)
CLK to Data Delay
75
80
ns
t
OH
(2)
Data Hold From CE, OE, or CLK
0
0
ns
t
DF
(3)
CE or OE to Data Float Delay
55
55
ns
t
LC
CLK Low Time
25
25
ns
t
HC
CLK High Time
25
25
ns
t
SCE
CE Setup Time to CLK (to guarantee proper counting)
35
60
ns
t
HCE
CE Hold Time to CLk (to guarantee proper counting)
0
0
ns
t
HOE
OE High Time (guarantees counter is reset)
25
25
ns
F
MAX
(4)
MAX Input Clock Frequency
10
8
10
MHz
AC Characteristics When Cascading
V
CC
= 3.3V
±
10%
Symbol
Description
Commercial
Industrial/Military
Units
Min
Max
Min
Max
t
CDF
(3)
CLK to Data Float Delay
60
60
ns
t
OCK
(2)
CLK to CEO Delay
55
60
ns
t
OCE
(2)
CE to CEO Delay
55
60
ns
t
OOE
(2)
RESET/OE to CEO Delay
40
45
ns
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AT17LV65A-10NC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10NI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10PC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10PI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10SC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
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