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參數(shù)資料
| 型號： | AT17LV65-10TQI |
| 廠商： | Atmel Corp. |
| 元件分類： | FPGA |
| 英文描述： | FPGA Configuration EEPROM Memory |
| 中文描述： | FPGA配置EEPROM存儲器 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 221K |
| 代理商： | AT17LV65-10TQI |
12
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
Notes:
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
Notes:
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
AC Characteristics
V
CC
Symbol
Description
AT17LV65/128/256
AT17LV512/010/002/040
Units
Commercial
Industrial
Commercial
Industrial
MinMax
T
OE
OE to Data Delay
50
55
50
55
ns
TCE
CE to Data Delay
60
55
60
ns
T
CAC
CLK to Data Delay
75
80
55
60
ns
T
OH
Data Hold from CE, OE, or CLK
0000
ns
TDF
CE or OE to Data Float Delay
55
50
ns
T
LC
CLK Low Time
25
ns
T
HC
CLK High Time
25
ns
T
SCE
CE Setup Time to CLK
(to guarantee proper counting)
35
60
30
35
ns
T
HCE
CE Hold Time from CLK
(to guarantee proper counting)
0000
ns
T
HOE
OE High Time (guarantees counter is reset)
25
ns
F
MAX
Maximum Clock Frequency
10
15
10
MHz
AC Characteristics when Cascading
VCC = 3.3V ± 10%
Symbol
Description
AT17LV65/128/256
AT17LV512/010/002/040
Units
Commercial
Industrial
Commercial
Industrial
Min
Max
Min
Max
Min
Max
Min
Max
T
CDF
(2)
CLK to Data Float Delay
60
50
ns
TOCK
CLK to CEO Delay
55
60
50
55
ns
T
OCE
CE to CEO Delay
55
60
35
40
ns
T
OOE
RESET/OE to CEO Delay
40
45
35
ns
FMAX
Maximum Clock Frequency
8
12.5
10
MHz
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV65A | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A_06 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10BJC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10BJI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10CC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
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