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參數(shù)資料
| 型號： | AT17LV256A-10JC |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | High-Speed CMOS Logic Dual 4-Input NAND Gates 14-SOIC -55 to 125 |
| 中文描述： | 256K X 1 CONFIGURATION MEMORY, PQCC20 |
| 封裝： | PLASTIC, MS-018AA, LCC-20 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 159K |
| 代理商： | AT17LV256A-10JC |
AT17A Series
3
Pin Configurations
PLCC/S
OIC
DIP
Pin
Pin
Name
I/O
Description
2
1
DATA
I/O
Three-state DATA output for reading. Input/Output pin for programming.
4
2
CLK
I
Clock input. Used to increment the internal address and bit counter for reading and
programming.
8
3
RESET/OE
RESET/Output Enable input (when SER_EN is High). A low level on both the CE and
RESET/OE inputs enables the data output driver. A high level on RESET/OE resets both
the address and bit counters. A logic polarity of this input is programmable as either
RESET/OE or RESET/OE. This document describes the pin as RESET/OE.
9
4
CE
I
Chip Enable input. Used for device selection. A low level on both CE and OE enables the
data output driver. A high level on CE disables both the address and bit counters and
forces te device into a low-power mode. Note this pin will not enable/disable the device in
2-wire serial mode (ie; when SER_EN is low).
10
5
GND
Ground pin
12
6
CEO
O
Chip Enable Out output. This signal is asserted low on the clock cycle following the last
bit read from the memory. It will stay low as long as CE and OE are both low. It will then
follow CE until OE goes high. Thereafter, CEO will stay high until the entire PROM is
read again and senses the status of RESET polarity.
A2
I
Device selection input, A2. This is used to enable (or select) the device during
programming and when SER_EN is low (see Programming Guide for more details).
18
7
SER_EN
I
Serial enable is normally high during FPGA loading operations. Bringing SER_EN low,
enables the 2-wire serial interface for programming.
20
8
V
CC
+3.3V/+5V power supply pin.
Absolute Maximum Ratings*
Operating Temperature..................................-55°C to +125°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature.....................................-65°C to +150°C
Voltage on Any Pin
with Respect to Ground............................. -0.1V to V
CC
+
0.5V
Supply Voltage (V
CC
) .......................................-0.5 V to + 7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260
°
C
ESD (R
ZAP
= 1.5K, C
ZAP
= 100 pF)................................. 2000V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17LV256A-10JI | FPGA Configuration EEPROM |
| AT17LV65A-10JC | High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-SOIC -55 to 125 |
| AT17LV65A-10JI | High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-SOIC -55 to 125 |
| AT17F080-30CC | FPGA CONFIGURATION FLASH MEMORY |
| AT17F040-30VJC | FPGA CONFIGURATION FLASH MEMORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV256A-10JI | 功能描述:IC SRL CONFG EEPROM 256K 20-PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標(biāo)準(zhǔn)包裝:98 系列:- 可編程類型:OTP 存儲容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件 |
| AT17LV256A-10NC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10NI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10PC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10PI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
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