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參數(shù)資料
| 型號(hào)： | AT17LV256-10CC |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | FPGA Configuration EEPROM Memory |
| 中文描述： | 256K X 1 CONFIGURATION MEMORY, DSO8 |
| 封裝： | 6 X 6 MM, 1.04 MM HEIGHT, 1.27 MM PITCH, LAP-8 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 221K |
| 代理商： | AT17LV256-10CC |
5
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
Block Diagram
Notes:
1. This pin is only available on AT17LV65/128/256 devices.
2. This pin is only available on AT17LV512/010/002 devices.
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter-
face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17LV series configurator. If CE is held High after
the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-
stated. When OE is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and
OE High, this document will describe RESET/OE.
POWER ON
RESET
SER_EN
WP1
(2)
WP2
(2)
(1)
READY
(2)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17LV256-10CI | FPGA Configuration EEPROM Memory |
| AT17LV256-10NC | FPGA Configuration EEPROM Memory |
| AT17LV256-10NI | FPGA Configuration EEPROM Memory |
| AT17LV128-10CC | FPGA Configuration EEPROM Memory |
| AT17LV128-10CI | FPGA Configuration EEPROM Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV256-10CI | 功能描述:IC SRL CONFIG EEPROM 256K 8-LAP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標(biāo)準(zhǔn)包裝:98 系列:- 可編程類型:OTP 存儲(chǔ)容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件 |
| AT17LV256-10CU | 功能描述:FPGA-配置存儲(chǔ)器 256KB EEPROM 8 PIN LAP 256 KB RoHS:否 制造商:Altera Corporation 存儲(chǔ)類型:Flash 存儲(chǔ)容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV256-10JC | 功能描述:FPGA-配置存儲(chǔ)器 256 KBIT EEPROM 8 PIN LAP 10MHZ RoHS:否 制造商:Altera Corporation 存儲(chǔ)類型:Flash 存儲(chǔ)容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV256-10JI | 功能描述:FPGA-配置存儲(chǔ)器 256 KBIT EEPROM 8 PIN LAP 10MHZ RoHS:否 制造商:Altera Corporation 存儲(chǔ)類型:Flash 存儲(chǔ)容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV256-10JL | 制造商:Atmel Corporation 功能描述:256K X 1 CONFIGURATION MEMORY, PQCC20 |
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