參數(shù)資料
型號(hào): AT17LV128A
廠(chǎng)商: Atmel Corp.
英文描述: High Speed CMOS Logic 4-Bit Parallel Access Register 16-TSSOP -55 to 125
中文描述: FPGA配置的EEPROM
文件頁(yè)數(shù): 7/11頁(yè)
文件大?。?/td> 159K
代理商: AT17LV128A
AT17A Series
7
.
AC Characteristics for AT17C256A
V
CC
= 5V
±
5% Commercial / V
CC
= 5V
±
10% Ind./Mil
.
Notes:
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pf.
3. Float delays are measured with 5 pF AC loads. Transition is measured
±
200 mV from steady-state active levels.
Symbol
Description
Commercial
Industrial/Military
Units
Min
Max
Min
Max
t
OE
(2)
OE to Data Delay
25
25
ns
t
CE
(2)
CE to Data Delay
45
45
ns
t
CAC
(2)
CLK to Data Delay
50
55
ns
t
OH
(2)
Data Hold From CE, OE, or CLK
0
0
ns
t
DF
(3)
CE or OE to Data Float Delay
50
50
ns
t
LC
CLK Low Time
20
20
ns
t
HC
CLK High Time
20
20
ns
t
SCE
CE Setup Time to CLK (to guarantee proper counting)
35
40
ns
t
HCE
CE Hold Time to CLk (to guarantee proper counting)
0
0
ns
t
HOE
OE High Time (guarantees counter is reset)
20
20
ns
F
MAX
MAX Input Clock Frequency
12.5
12.5
MHz
AC Characteristics for AT17C256A When Cascading
V
CC
= 5V
±
5% Commercial / V
CC
= 5V
±
10% Ind./Mil
Symbol
Description
Commercial
Industrial/Military
Units
Min
Max
Min
Max
t
CDF
(3)
CLK to Data Float Delay
50
50
ns
t
OCK
(2)
CLK to CEO Delay
35
40
ns
t
OCE
(2)
CE to CEO Delay
35
35
ns
t
OOE
(2)
RESET/OE to CEO Delay
30
35
ns
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