參數(shù)資料
型號: AT17LV128A-10CI
廠商: Atmel Corp.
元件分類: FPGA
英文描述: FPGA Configuration EEPROM Memory
中文描述: FPGA配置EEPROM存儲器
文件頁數(shù): 5/24頁
文件大小: 221K
代理商: AT17LV128A-10CI
13
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
Notes:
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
Notes:
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
AC Characteristics
V
CC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial
Symbol
Description
AT17LV65/128/256
AT17LV512/010/002/040
Units
Commercial
Industrial
Commercial
Industrial
MinMax
T
OE
OE to Data Delay
30
35
30
35
ns
TCE
CE to Data Delay
45
ns
T
CAC
CLK to Data Delay
50
55
50
ns
T
OH
Data Hold from CE, OE, or CLK
0
ns
CE or OE to Data Float Delay
50
ns
T
LC
CLK Low Time
20
ns
T
HC
CLK High Time
20
ns
T
SCE
CE Setup Time to CLK (to guarantee proper
counting)
35
40
20
25
ns
T
HCE
CE Hold Time from CLK (to guarantee proper
counting)
00
ns
T
HOE
OE High Time (guarantees counter is reset)
20
ns
F
MAX
Maximum Clock Frequency
12.5
15
MHz
AC Characteristics when Cascading
VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial
Symbol
Description
AT17LV65/128/256
AT17LV512/010/002/040
Units
Commercial
Industrial
Commercial
Industrial
MinMax
Min
Max
MinMax
T
CDF
CLK to Data Float Delay
50
ns
TOCK
CLK to CEO Delay
35
40
35
40
ns
T
OCE
CE to CEO Delay
35
ns
T
OOE
RESET/OE to CEO Delay
30
35
30
ns
FMAX
Maximum Clock Frequency
10
12.5
MHz
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AT17LV128A-10JI 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory
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