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參數(shù)資料
| 型號(hào)： | AT17LV010A-10SC |
| 廠商： | Atmel Corp. |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA Configuration EEPROM Memory |
| 中文描述： | FPGA配置EEPROM存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大小： | 113K |
| 代理商： | AT17LV010A-10SC |
AT17C/LV512/010
4
FPGA Master Serial Mode Summary
The I/O and logic functions of the FPGA and their associ-
ated interconnections are established by a configuration
program. The program is loaded either automatically upon
power up, or on command, depending on the state of the
three FPGA mode pins. In Master Mode, the FPGA auto-
matically loads the configuration program from an external
memory. The Serial Configuration EEPROM has been
designed for compatibility with the Master Serial Mode.
Cascading Serial Configuration
EEPROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded Configurators provide additional memory.
As the last bit from the first Configurator is read, the clock
signal to the Configurator asserts its CEO output Low and
disables its DATA line. The second Configurator recog-
nizes the Low level on its CE input and enables its DATA
output.
Figure 1.
Condition 1 Connection
After configuration is complete, the address counters of all
cascaded Configurators are reset if the reset signal drives
the RESET/OE on each Configurator to its active (High)
level.
If the address counters are not to be reset upon comple-
tion, then the RESET/OE inputs can be tied to ground. For
more details, please reference the AT17C Series Program-
ming Guide.
Programming Mode
The programming mode is entered by bringing SER_EN
Low. In this mode the chip can be programmed by the 2-
wire interface. The programming is done at V
CC
supply
only. Programming super voltages are generated inside the
chip. See the Programming Specification for Atmel's Con-
figuration Memories Application Note for further informa-
tion. The AT17C Series parts are read/write at 5V nominal.
The AT17LV parts are read/write at 3.3V nominal.
AT17C/LVXXX Reset Polarity
The AT17C/LVXXX lets the user choose the reset polarity
as either RESET/OE or RESET/OE.
Standby Mode
The AT17C/LVXXX enters a low-power standby mode
whenever CE is asserted High. In this mode, the Configura-
tor consumes less than 0.5mA at 5.0 volts. The output
remains in a high impedance state regardless of the state
of the OE input.
Operating Conditions
Symbol
Description
AT17CXXX
AT17LVXXX
Units
Min/Max
Min/Max
V
CC
Commercial
Supply voltage relative to GND
-0°C to +70°C
4.75 / 5.25
3.0 / 3.6
V
Industrial
Supply voltage relative to GND
-40°C to +85°C
4.5 / 5.5
3.0 / 3.6
V
Military
Supply voltage relative to GND
-55°C to +125°C
4.5 / 5.5
3.0 / 3.6
V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17LV010A-10SI | FPGA Configuration EEPROM Memory |
| AT17LV010A-10TQC | FPGA Configuration EEPROM Memory |
| AT17LV010A-10TQI | FPGA Configuration EEPROM Memory |
| AT17LV010-10PC | FPGA Configuration EEPROM Memory |
| AT17LV010-10PI | FPGA Configuration EEPROM Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV010A-10SI | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A-10TQC | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A-10TQI | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010-W | 功能描述:FPGA-配置存儲(chǔ)器 FPGA CONFIG SERIAL EEPROM, 1M, 3.3V - DIE WAFER RoHS:否 制造商:Altera Corporation 存儲(chǔ)類(lèi)型:Flash 存儲(chǔ)容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV020 | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:2-megabit FPGA Configuration EEPROM Memory |
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