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參數(shù)資料
| 型號： | AT17LV010-10DP-E |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | Space FPGA Configuration EEPROM |
| 中文描述： | 1M X 1 CONFIGURATION MEMORY, DFP28 |
| 封裝： | 0.400 INCH, DFP-28 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 179K |
| 代理商： | AT17LV010-10DP-E |
3
A717LV010-10DP
4265B–AERO–06/04
Block Diagram
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter-
face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17LV010-10DP configurator. If CE is held High
after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-
stated. When OE is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and
OE High, this document will describe RESET/OE.
POWER ON
RESET
SER_EN
WP1
WP2
READY
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17LV010-10DP-M | Space FPGA Configuration EEPROM |
| AT17LV010-10DP-SV | Space FPGA Configuration EEPROM |
| AT17LV256A | 256K FPGA Configuration EEPROM Memory(256K 現(xiàn)場可編程門陣列（FPGA）配置EEPROM存儲器) |
| AT17LV512 | 512K FPGA Configuration EEPROM Memory(512K 現(xiàn)場可編程（FPGA）配置EEPROM存儲器) |
| AT22LV10 | Low-Voltage UV Erasable Programmable Logic Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV010-10DP-M | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Space FPGA Configuration EEPROM |
| AT17LV010-10DP-MQ | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Space FPGA Configuration EEPROM |
| AT17LV010-10DP-SV | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Space FPGA Configuration EEPROM |
| AT17LV010-10JC | 功能描述:FPGA-配置存儲器 CONFIG SERIAL EEPROM 1M 3.3V - 10MHZ RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV010-10JC SL383 | 制造商:Atmel Corporation 功能描述:EEPROM SERL-2WIRE 1MBIT 1M X 1 3.3V/5V 20PLCC - Tape and Reel |
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