參數(shù)資料
型號: AT17F080-30TQC
廠商: ATMEL CORP
元件分類: DRAM
英文描述: FPGA CONFIGURATION FLASH MEMORY
中文描述: 8M X 1 CONFIGURATION MEMORY, PQFP44
封裝: 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026ACB, TQFP-44
文件頁數(shù): 4/19頁
文件大?。?/td> 307K
代理商: AT17F080-30TQC
4
3039I–CNFG–2/05
AT17F040/080
3.
Block Diagram
4.
Device Description
The control signals for the configuration memory device (CE, RESET/OE and CLK) interface
directly with the FPGA device control signals. All FPGA devices can control the entire configura-
tion process and retrieve data from the configuration device without requiring an external
intelligent controller.
The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the
address counter. When RESET/OE is driven Low, the configuration device resets its address
counter and tri-states its DATA pin. The CE pin also controls the output of the AT17F Series
Configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the
DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA
output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and
the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device tri-states
the DATA pin to avoid contention with other configurators. Upon power-up, the address counter
is automatically reset.
Config. Page
Select
Power-on
Reset
Flash
Memory
Clock/Oscillator
Logic
2-wire Serial Programming
Serial Download Logic
Control Logic
CLK
CEO(A2)
DATA
CE
RESET/OE
SER_EN
CE/WE/OE
Data
Address
READY
PAGE_EN
PAGESEL0
PAGESEL1
Reset
相關(guān)PDF資料
PDF描述
AT17F080-30TQI FPGA CONFIGURATION FLASH MEMORY
AT17F040-30JC FPGA CONFIGURATION FLASH MEMORY
AT17F040-30JI FPGA CONFIGURATION FLASH MEMORY
AT17F040-30JU FPGA CONFIGURATION FLASH MEMORY
AT17F080 FPGA CONFIGURATION FLASH MEMORY
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