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參數(shù)資料
| 型號： | AT17C65A-10JI |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | FPGA Configuration EEPROM |
| 中文描述： | 64K X 1 CONFIGURATION MEMORY, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大小： | 159K |
| 代理商： | AT17C65A-10JI |
AT17A Series
4
FPGA Master Serial Mode Summary
The I/O and logic functions of the FPGA and their associ-
ated interconnections are established by a configuration
program. The program is loaded either automatically upon
power up, or on command, depending on the state of the
three FPGA mode pins. In Master Mode, the FPGA auto-
matically loads the configuration program from an external
memory. The Serial Configuration EEPROM has been
designed for compatibility with the Master Serial Mode.
Cascading Serial Configuration
EEPROMs (AT17C/LV256A)
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded Configurators provide additional memory
(17C/LV128/256A only).
After the last bit from the first Configurator is read, the next
clock signal to the Configurator asserts its CEO output Low
and disables its DATA line. The second Configurator rec-
ognizes the low level on its CE input and enables its DATA
output.
Figure 1.
Condition 1 Connection
After configuration is complete, the address counters of all
cascaded Configurators are reset if the reset signal drives
the RESET/OE on each Configurator Active.
If the address counters are not to be reset upon comple-
tion, then the RESET/OE inputs can be tied to ground. For
more details, please reference the AT17C Series Program-
ming Guide
Programming Mode
The programming mode is entered by bringing SER_EN
low. In this mode the chip can be programmed by the 2-
wire interface. The programming is done at V
CC
supply
only. Programming super voltages are generated inside the
chip. See the Programming Specification for Atmel’s Con-
figuration Memories Application Note for further informa-
tion. The AT17C Series parts are read/write at 5V nominal.
The AT17LV parts are read/write at 3.0V nominal.
AT17C/LVxxx Reset Polarity
The AT17C/LVxxxA lets the user choose the reset polarity
as either RESET/OE or RESET/OE.
Standby Mode
The AT17C/LVxxxA enters a low-power standby mode
whenever CE is asserted high. In this mode, the Configura-
tor consumes less than 1.0 mA of current. The output
remains in a high-impedance state regardless of the state
of the OE input.
CS
REBOOT
M2
M1
M0
FPGA
D0
CCLK
CON
FLEX DEVICE
SERIAL
EEPROM
DATA
CLK
CE
SER_EN
RESET/OE
AT17CXX
V
CC
FLEX 10K, FLEX 16K
(CLK REQUIRED)
Operating Conditions
Symbol
Description
AT17Cxxx
AT17LVxxx
Units
Min/Max
Min/Max
V
CC
Commercial
Supply voltage relative to GND
-0
°
C to +70
°
C
4.75/5.25
3.0/3.6
V
Industrial
Supply voltage relative to GND
-40
°
C to +85C
°
4.5/5.5
3.0/3.6
V
Military
Supply voltage relative to GND
-55
°
C to +125C
4.5/5.5
3.0/3.6
V
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| AT17LV128A | High Speed CMOS Logic 4-Bit Parallel Access Register 16-TSSOP -55 to 125 |
| AT17LV65A | High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-PDIP -55 to 125 |
| AT17A | FPGA Configuration EEPROM |
| AT17LV256A-10JC | High-Speed CMOS Logic Dual 4-Input NAND Gates 14-SOIC -55 to 125 |
| AT17LV256A-10JI | FPGA Configuration EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17CXXXA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA Configuration EEPROM 65K. 128K and 256K |
| AT-17D | 功能描述:揚(yáng)聲器與變頻器 PZ 80dB 4000Hz 9Vpp RoHS:否 制造商:PUI Audio 產(chǎn)品:Speakers 類型:Electromagnetic 頻率:900 Hz to 12 kHz 聲壓級:88 dBA 阻抗:8 Ohms 功率額定值:1.2 W 形狀:Round 端接類型:Solder Pad 直徑:15 mm 長度: 寬度: 深度:4.4 mm 磁體材料:Neodymium Iron Boran (NdFeB) 圓錐體材料:Mylar |
| AT17F040 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration Flash Memory |
| AT17F040_08 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration Flash Memory |
| AT17F040-30CC | 功能描述:FPGA-配置存儲器 8-LAP 4MBx1 5V RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
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