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參數(shù)資料
| 型號(hào)： | AT17C512-10CC |
| 英文描述： | Configuration EEPROM |
| 中文描述： | 配置EEPROM |
| 文件頁(yè)數(shù)： | 3/18頁(yè) |
| 文件大?。?/td> | 236K |
| 代理商： | AT17C512-10CC |
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3
AT17C512/010/LV512/010
0944E
–
12/01
Block Diagram
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter-
face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17 Series Configurator. If CE is held High after the
RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated.
When OE is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and
OE High, this document will describe RESET/OE.
EEPROM
CELL
MATRIX
ROW
DECODER
COLUMN
DECODER
TC
CE
CLK
READY
RESET/OE
CEO(A2)
DATA
BIT
COUNTER
OSC
OSC
CONTROL
PROGRAMMING
DATA SHIFT
REGISTER
PROGRAMMING
MODE LOGIC
ROW
ADDRESS
COUNTER
POWER ON
RESET
SER_EN
WP1
WP2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17C512-10CI | Configuration EEPROM |
| AT17C512-10PC | Configuration EEPROM |
| AT17C512-10PI | Configuration EEPROM |
| AT17C512A-10PC | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| AT17C512A-10PI | Configuration EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17C512-10CI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EEPROM |
| AT17C512-10JC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration E2PROM Memory |
| AT17C512-10JI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration E2PROM Memory |
| AT17C512-10PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EEPROM |
| AT17C512-10PI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EEPROM |
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