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參數(shù)資料
| 型號： | AT17C256-10PC |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | FPGA Configuration E2PROM |
| 中文描述： | 256K X 1 CONFIGURATION MEMORY, PDIP8 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-8 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大小： | 149K |
| 代理商： | AT17C256-10PC |
AT17 Series
9
AC Characteristics
V
CC
= 3.3V
±
10%
Notes:
1. Preliminary specifications for military operating range only.
2. AC test lead = 50 pf.
3. Float delays are measured with 5 pF AC loads. Transition is measured
±
200 mV afrom steady state active levels.
4. During cascade F
MAX
= 8 MHz.
Symbol
Description
Commercial
Industrial/Military
Units
Min
Max
Min
Max
T
OE
T
CE
T
CAC
T
OH
T
DF
T
LC
T
HC
T
SCE
T
HCE
T
HOE
F
MAX
(2)
OE to Data Delay
40
45
ns
(2)
CE to Data Delay
60
60
ns
(2)
CLK to Data Delay
75
80
ns
(2)
Data Hold From CE, OE, or CLK
0
0
ns
(3)
CE or OE to Data Float Delay
55
55
ns
CLK Low Time
25
25
ns
CLK High Time
25
25
ns
CE Setup Time to CLK (to guarantee proper counting)
35
60
ns
CE Hold Time to CLk (to guarantee proper counting)
0
0
ns
OE High Time (guarantees counter is reset)
25
25
ns
(4)
MAX Input Clock Frequency
10
8
10
MHz
AC Characteristics When Cascading
V
CC
= 3.3V
±
10%
Symbol
Description
Commercial
Industrial/Military
Units
Min
Max
Min
Max
T
CDF
T
OCK
T
OCE
T
OOE
(3)
CLK to Data Float Delay
60
60
ns
(2)
CLK to CEO Delay
55
60
ns
(2)
CE to CEO Delay
55
60
ns
(2)
RESET/OE to CEO Delay
40
45
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17C256-10PI | FPGA Configuration E2PROM |
| AT17C256-10SC | FPGA Configuration E2PROM |
| AT17C256-10SI | FPGA Configuration E2PROM |
| AT17C65 | FPGA Configuration E2PROM |
| AT17C65-10JC | FPGA Configuration E2PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17C25610PI | 制造商:ALTERA 功能描述:New |
| AT17C256-10PI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration E2PROM |
| AT17C256-10SC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration E2PROM |
| AT17C256-10SI | 制造商:Atmel Corporation 功能描述:Serial EEPROM, 20 Pin, Plastic, SOP |
| AT17C256A | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM |
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