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參數(shù)資料
| 型號(hào)： | AT17C256-10JC |
| 廠(chǎng)商： | ATMEL CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | Surface Mount Resistors Thick Film Chip Resistors |
| 中文描述： | 256K X 1 CONFIGURATION MEMORY, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 149K |
| 代理商： | AT17C256-10JC |
AT17 Series
3
Pin Configurations
PLCC/
SOIC
DIP
Pin
Pin
Name
I/O
Description
2
1
DATA
I/O
Three-state DATA output for reading. Input/Output pin for programming.
4
2
CLK
I
Clock input. Used to increment the internal address and bit counter for reading
and programming.
6
3
RESET/OE
RESET/Output Enable input (when SER_EN is High). A Low level on both the
CE and RESET/OE inputs enables the data output driver. A High level on
RESET/OE resets both the addresss and bit counters. A logic polarity of this
input is programmable as either RESET/OE or RESET/OE. This document
describes the pin as RESET/OE.
8
4
CE
I
Chip Enable input. Used for device selection. A Low level on both CE and OE
enables the data output driver. A High level on CE disables both the address
and bit counters and forces te device into a low power mode. Note this pin will
not enable/disable the device in 2-wire Serial mode (ie; when SER_EN is Low).
10
5
GND
Ground Pin
14
6
CEO
O
Chip Enable Out output. This signal is asserted Low on the clock cycle following
the last bit read from the memory. It will stay Low as long as CE and OE are
both Low. It will then follow CE until OE goes High. Thereafter CEO will stay
High until the entire PROM is read again and senses the status of RESET
polarity.
A2
I
Device selection input, A2. This is used to enable (or select) the device during
programming and when SER_EN is Low (see Programming Guide for more
details).
17
7
SER_EN
I
Serial enable is normally high during FPGA loading operations. Bringing
SER_EN low, enables the 2-wire serial interface for programming.
20
8
V
CC
+3.3V/+5V power supply pin.
Absolute Maximum Ratings*
Operating Temperature.........................-55°C to +125°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature............................-65°C to +150°C
Voltage on Any Pin
with Respect to Ground.................... -0.1V to V
CC +
0.5V
Supply Voltage (Vcc)..............................-0.5 V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.)...260
°
C
ESD (R
ZAP
= 1.5K, C
ZAP
= 100pF) ........................2000V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17C256-10JI | FPGA Configuration E2PROM |
| AT17C256-10PC | FPGA Configuration E2PROM |
| AT17C256-10PI | FPGA Configuration E2PROM |
| AT17C256-10SC | FPGA Configuration E2PROM |
| AT17C256-10SI | FPGA Configuration E2PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17C25610JI | 制造商:ATMEL 功能描述:New |
| AT17C256-10JI | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:FPGA Configuration E2PROM |
| AT17C256-10NC | 功能描述:FPGA-配置存儲(chǔ)器 ASICS RoHS:否 制造商:Altera Corporation 存儲(chǔ)類(lèi)型:Flash 存儲(chǔ)容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17C256-10NI | 功能描述:FPGA-配置存儲(chǔ)器 RO 556-AT17LV25610NI RoHS:否 制造商:Altera Corporation 存儲(chǔ)類(lèi)型:Flash 存儲(chǔ)容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17C256-10PC | 功能描述:FPGA-配置存儲(chǔ)器 256K10MHz 5V RoHS:否 制造商:Altera Corporation 存儲(chǔ)類(lèi)型:Flash 存儲(chǔ)容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
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