- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381395 > AT17C020 (Atmel Corp.) 2M bit FPGA Configuration EEPROM Memory(2M位 FPGA配置EEPROM存儲(chǔ)器) PDF資料下載
參數(shù)資料
| 型號(hào)： | AT17C020 |
| 廠商： | Atmel Corp. |
| 英文描述： | 2M bit FPGA Configuration EEPROM Memory(2M位 FPGA配置EEPROM存儲(chǔ)器) |
| 中文描述： | 200萬位FPGA配置存儲(chǔ)器（200萬位的FPGA配置的EEPROM存儲(chǔ)器） |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 204K |
| 代理商： | AT17C020 |
AT17C/LV020
4
Pin Configurations
20-pin
PLCC
Name
I/O
Description
2
DATA
I/O
Three-state DATA output for configuration. Open-collector bidirectional pin for programming.
4
CLK
I
Clock input. Used to increment the internal address and bit counter for reading and
programming.
6
RESET/OE
I
RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and
RESET/OE inputs enables the data output driver. A High level on RESET/OE resets both the
address and bit counters. The logic polarity of this input is programmable as either RESET/OE
or RESET/OE. This document describes the pin as RESET/OE.
8
CE
I
Chip Enable input. Used for device selection. A Low level on both CE and OE enables the data
output driver. A High level on CE disables both the address and bit counters and forces the
device into a low power standby mode. Note that this pin will not enable/disable the device in
the 2-wire Serial Programming Mode (i.e., when SER_EN is Low).
10
GND
Ground pin. A 0.2 μF decoupling capacitor between VCC and GND is recommended.
14
CEO
O
Chip Enable Output. This signal is asserted Low on the clock cycle following the last bit read
from the memory. It will stay Low as long as CE and OE are both Low. It will then follow CE until
OE goes High. Thereafter, CEO will stay High until the entire EEPROM is read again.
A2
I
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low; see the “Programming Specification” application note for more
details).
15
READY
O
Open collector reset state indicator. Driven Low during power-up reset, released when power-
up is complete. (Recommend a 4.7 K
pull-up on this pin if used).
17
SER_EN
I
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the 2-wire Serial Programming Mode.
20
VCC
+3.3V/+5V power supply pin.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17LV020 | 2M bit FPGA Configuration EEPROM Memory(2M位 FPGA配置EEPROM存儲(chǔ)器) |
| AT17C128-10JC | FPGA Configuration E2PROM |
| AT17LV65-10JC | FPGA Configuration E2PROM |
| AT17LV65-10JI | FPGA Configuration E2PROM |
| AT17LV65-10PC | FPGA Configuration E2PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17C020-10JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EEPROM |
| AT17C020-10JI | 功能描述:1C SERIAL CONFIG PROM 2M 20PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標(biāo)準(zhǔn)包裝:98 系列:- 可編程類型:OTP 存儲(chǔ)容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件 |
| AT17C020A | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17C020A-10JC | 功能描述:IC SERIAL CONFIG PROM 2M 20PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標(biāo)準(zhǔn)包裝:98 系列:- 可編程類型:OTP 存儲(chǔ)容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件 |
| AT17C020A-10JI | 功能描述:IC SERIAL CONFIG PROM 2M 20PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標(biāo)準(zhǔn)包裝:98 系列:- 可編程類型:OTP 存儲(chǔ)容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。