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參數(shù)資料
| 型號： | AT17C010A-10QC |
| 英文描述： | SERIAL EEPROM|CMOS|TQFP|32PIN|PLASTIC |
| 中文描述： | 串行EEPROM的|的CMOS | TQFP封裝| 32腳|塑料 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大小： | 236K |
| 代理商： | AT17C010A-10QC |
12
AT17C512/010/LV512/010
0944E
–
12/01
Notes:
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.
Notes:
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.
AC Characteristics for AT17LV512/010
V
CC
= 3.3V ± 10%
Symbol
Description
Commercial
Industrial/Military
(1)
Units
Min
Max
Min
Max
T
OE
(2)
OE to Data Delay
50
55
ns
T
CE
(2)
CE to Data Delay
55
60
ns
T
CAC
(2)
CLK to Data Delay
55
60
ns
T
OH
Data Hold From CE, OE, or CLK
0
0
ns
T
DF
(3)
CE or OE to Data Float Delay
50
50
ns
T
LC
CLK Low Time
25
25
ns
T
HC
CLK High Time
25
25
ns
T
SCE
CE Setup Time to CLK (to guarantee proper counting)
30
35
ns
T
HCE
CE Hold Time from CLK (to guarantee proper counting)
0
0
ns
T
HOE
OE High Time (guarantees counter is reset)
25
25
ns
F
MAX
MAX Input Clock Frequency
15
10
MHz
AC Characteristics for AT17LV512/010 when Cascading
V
CC
= 3.3V
±
10%
Symbol
Description
Commercial
Industrial/Military
(1)
Units
Min
Max
Min
Max
T
CDF
(3)
CLK to Data Float Delay
50
50
ns
T
OCK
(2)
CLK to CEO Delay
50
55
ns
T
OCE
(2)
CE to CEO Delay
35
40
ns
T
OOE
(2)
RESET/OE to CEO Delay
35
35
ns
F
MAX
MAX Input Clock Frequency
12.5
10
MHz
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| AT17C010A-10QI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SERIAL EEPROM|CMOS|TQFP|32PIN|PLASTIC |
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| AT17C020A | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
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