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參數(shù)資料
| 型號： | AT17C010A-10JC |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | FPGA Serial Configuration Memories |
| 中文描述： | 1M X 1 CONFIGURATION MEMORY, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 134K |
| 代理商： | AT17C010A-10JC |
AT17C/LV/512A/010A
4
Pin Configurations
Pin Number
(20-Pin PLCC)
Pin Name
Pin Type
Description
2
DATA
Output
Serial data output.
4
DCLK
I/O
Clock output or clock input. Rising edges on DCLK increment the internal address
counter and present the next bit of data to the DATA pin. The counter is incremented
only if the OE input is held high, the nCS input is held low, and all configuration data
has not been transferred to the target device (otherwise, in FPGA 10K master mode,
the DCLK pin drives low).
5
WP1
Input
WRITE PROTECT (1). Used to protect portions of memory during programming. See
programming guide for details.
8
RESET/OE
Input
Output enable (active high) and reset (active low). A low logic level resets the address
counter. A high logic level enables DATA and permits the address counter to count. In
the mode, if this pin is low (reset), the internal oscillator becomes inactive and DCLK
drives low.
9
nCS
Input
Chip select input (active low). A low input allows DCLK to increment the address
counter and enables DATA to drive out. If the AT17A Series is reset with nCS low, the
device initializes as the first device in a daisy-chain. If the AT17A Series is reset with
nCS high, the device initializes as the next AT17A Series device in the chain
10
GND
Ground
A 0.2
μ
F decoupling capacitor should be placed between the V
CC
and GND pins.
12
nCASC
Output
Cascade select output (active low). This output goes low when the address counter
has reached its maximum value. In a daisy-chain of AT17A Series devices, the
nCASC pin of one device is usually connected to the nCS input pin of the next device
in the chain, which permits DCLK to clock data from the next AT17A Series device in
the chain.
A2
Input
Device selection input, A2. This is used to enable (or select) the device during
programming, when SER_EN is Low (see Programming Guide for more details)
15
READY
Output
Open collector reset state indicator. Driven Low during power-up reset, released when
power-up is complete. (Recommend a 4.7K
Pull-up on this pin if used).
18
SER_EN
Input
Serial enable is normally high during FPGA loading operations. Bringing SER_EN
Low, enables the two wire serial interface mode for programming.
20
V
CC
Power
Power pin.
Absolute Maximum Ratings*
Operating Temperature.................................. -55
°
C to +125
°
C
*NOTICE:
Stresses beyond those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional
operation of the device at these or any other condi-
tions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Rat-
ings conditions for extended periods of time may
affect device reliability.
Storage Temperature..................................... -65
°
C to +150
°
C
Voltage on Any Pin
with Respect to Ground.............................-0.1V to V
CC
+ 0.5V
Supply Voltage (V
CC
) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 s @ 1/16 in.)..................260
°
C
ESD (R
ZAP
= 1.5K, C
ZAP
= 100 pF)................................ 2000V
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| AT17C010A-10JI | FPGA Serial Configuration Memories |
| AT17LV010A-10JC | FPGA Serial Configuration Memories |
| AT17LV010A-10JI | FPGA Serial Configuration Memories |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17C010A-10JI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Serial Configuration Memories |
| AT17C010A-10PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SERIAL EEPROM|CMOS|DIP|8PIN|PLASTIC |
| AT17C010A-10PI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EEPROM |
| AT17C010A-10QC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SERIAL EEPROM|CMOS|TQFP|32PIN|PLASTIC |
| AT17C010A-10QI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SERIAL EEPROM|CMOS|TQFP|32PIN|PLASTIC |
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