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參數(shù)資料
| 型號(hào)： | AT17C010-10PI |
| 英文描述： | Configuration EEPROM |
| 中文描述： | 配置EEPROM |
| 文件頁(yè)數(shù)： | 4/18頁(yè) |
| 文件大?。?/td> | 236K |
| 代理商： | AT17C010-10PI |
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4
AT17C512/010/LV512/010
0944E
–
12/01
Note:
1. This pin is not available on the 8-lead packages.
Pin Description
8
PDIP/
LAP
Pin
20
PLCC
Pin
Name
I/O
Description
1
2
DATA
I/O
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
2
4
CLK
I
Clock input. Used to increment the internal address and bit counter for reading and
programming.
5
WP1
(1)
I
WRITE PROTECT (1). Used to protect portions of memory during programming.
Disabled by default due to internal pull-down resistor. This input pin is not used
during FPGA loading operations.
3
6
RESET/OE
I
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low
level on RESET/OE resets both the address and bit counters. A High level (with CE
Low) enables the data output driver. The logic polarity of this input is programmable
as either RESET/OE or RESET/OE. For most applications, RESET should be
programmed active Low. This document describes the pin as RESET/OE.
7
WP2
(1)
I
WRITE PROTECT (2). Used to protect portions of memory during programming.
Disabled by default due to internal pull-down resistor. This input pin is not used
during FPGA loading operations.
4
8
CE
I
Chip Enable input (active Low). A Low level (with OE High) allows DCLK to
increment the address counter and enables the data output driver. A High level on
CE disables both the address and bit counters and forces the device into a low-
power standby mode. Note that this pin will
not
enable/disable the device in the 2-
wire Serial Programming mode ( SER_EN Low).
5
10
GND
Ground pin. A 0.2 μF decoupling capacitor between
V
CC
and GND is
recommended.
6
14
CEO
O
Chip Enable Output (active Low). This output goes Low when the address counter
has reached its maximum value. In a daisy chain of AT17 Series devices, the CEO
pin of one device must be connected to the CE input of the next device in the chain.
It will stay Low as long as CE is low and OE is High. It will then follow CE until OE
goes Low; thereafter, CEO will stay High until the entire EEPROM is read again.
A2
I
Device selection input, A2. This is used to enable (or select) the device during
programming (i.e., when SER_EN is Low). A2 has an internal pulldown resistor.
15
READY
(1)
O
Open collector reset state indicator. Driven Low during power-up reset, released
(tri-stated) when power-up is complete. (Recommend a 4.7 k
pull-up on this pin if
used).
7
17
SER_EN
I
Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the 2-wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to V
CC
.
8
20
V
CC
+3.3V/+5V power supply pin.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17C010A-10PC | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| AT17C010A-10PI | Configuration EEPROM |
| AT17C010A-10QC | SERIAL EEPROM|CMOS|TQFP|32PIN|PLASTIC |
| AT17C010A-10QI | SERIAL EEPROM|CMOS|TQFP|32PIN|PLASTIC |
| AT17C020-10JC | Configuration EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17C010A | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17C010A-10JC | 制造商:Atmel Corporation 功能描述:1M X 1 CONFIGURATION MEMORY, PQCC20 |
| AT17C010A-10JI | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:FPGA Serial Configuration Memories |
| AT17C010A-10PC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SERIAL EEPROM|CMOS|DIP|8PIN|PLASTIC |
| AT17C010A-10PI | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Configuration EEPROM |
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