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參數(shù)資料
| 型號： | AT17C010-10CI |
| 英文描述： | Configuration EEPROM |
| 中文描述： | 配置EEPROM |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 236K |
| 代理商： | AT17C010-10CI |
5
AT17C512/010/LV512/010
0944E
–
12/01
FPGA Master Serial
Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configura-
tion program. The program is loaded either automatically upon power-up, or on
command, depending on the state of the FPGA mode pins. In Master Mode, the FPGA
automatically loads the configuration program from an external memory. The AT17
Serial Configuration EEPROM has been designed for compatibility with the Master
Serial Mode.
This document discusses the AT40K, AT40KAL and AT94KAL applications, as well as
Xilinx applications.
Control of
Configuration
Most connections between the FPGA device and the AT17 Serial EEPROM are simple
and self-explanatory:
The DATA output of the AT17 Series Configurator drives DIN of the FPGA devices.
The master FPGA CCLK output drives the CLK input of the AT17 Series
Configurator.
The CEO output of any AT17 Series Configurator drives the CE input of the next
Configurator in a cascade chain of EEPROMs.
SER_EN must be connected to V
CC
(except during ISP).
The READY pin is available as an open-collector indicator of the device
’
s reset
status; it is driven Low while the device is in its power-on reset cycle and released
(tri-stated) when the cycle is complete.
Cascading Serial
Configuration
EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configu-
ration memories, cascaded Configurators provide additional memory.
As the last bit from the first Configurator is read, the clock signal to the Configurator
asserts its CEO output Low and disables its DATA line driver. The second Configurator
recognizes the Low level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded Configurators are
reset if the RESET/OE on each Configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input
can be tied to its inactive (High) level.
AT17 Series Reset
Polarity
The AT17 Series Configurator allows the user to program the reset polarity as either
RESET/OE or RESET/OE. This feature is supported by industry-standard programmer
algorithms.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the 2-wire serial bus. The programming is done at V
CC
supply only.
Programming super voltages are generated inside the chip. The AT17C parts are
read/write at 5V nominal. The AT17LV parts are read/write at 3.3V nominal.
Standby Mode
The AT17C/LV512/010 Series Configurator enters a low-power standby mode when-
ever CE is asserted High. In this mode, the Configurator consumes less than 0.5 mA of
current at 5V. The output remains in a high-impedance state regardless of the state of
the OE input.
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PDF描述 |
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| AT17C010-10PC | Configuration EEPROM |
| AT17C010-10PI | Configuration EEPROM |
| AT17C010A-10PC | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| AT17C010A-10PI | Configuration EEPROM |
| AT17C010A-10QC | SERIAL EEPROM|CMOS|TQFP|32PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17C010-10JC | 功能描述:FPGA-配置存儲器 1M 15MHz 5V RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17C010-10JI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration E2PROM Memory |
| AT17C010-10PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EEPROM |
| AT17C010-10PI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EEPROM |
| AT17C010A | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
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