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參數(shù)資料
| 型號： | AT17C002-10BJI |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | FPGA Configuration EEPROM Memory |
| 中文描述： | 2M X 1 CONFIGURATION MEMORY, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 255K |
| 代理商： | AT17C002-10BJI |
4
AT17C/LV002
2281D
–
12/01
Note:
1. This pin is not available on the 8-lead packages.
Pin Configurations
8
LAP
Pin
20
PLCC
Pin
44
TQFP
Pin
44
PLCC
Pin
Name
I/O
Description
1
2
40
2
DATA
I/O
Three-state DATA output for configuration. Open-collector bi-directional
pin for programming.
2
4
43
5
CLK
I
Clock input. Used to increment the internal address and bit counter for
reading and programming.
–
5
7
7
WP1
(1)
I
WRITE PROTECT (1). Used to protect portions of memory during
programming. Disabled by default due to internal pull-down resistor.
This input pin is not used during FPGA loading operations.
3
6
13
19
RESET/OE
I
Output Enable (active High) and RESET (active Low) when SER_EN is
High. A Low level on RESET/OE resets both the address and bit
counters. A High level (with CE Low) enables the data output driver. The
logic polarity of this input is programmable as either RESET/OE or
RESET/OE. For most applications, RESET should be programmed
active Low. This document describes the pin as RESET/OE.
4
8
15
21
CE
I
Chip Enable input (active Low). A Low level (with OE High) allows DCLK
to increment the address counter and enables the data output driver. A
High level on CE disables both the address and bit counters and forces
the device into a low-power standby mode. Note that this pin will
not
enable/disable the device in the 2-wire Serial Programming mode
(SER_EN Low).
5
10
18
24
GND
Ground pin. A 0.2 μF decoupling capacitor between
V
CC
and GND is
recommended.
6
14
21
27
CEO
O
Chip Enable Output (active Low). This output goes Low when the
address counter has reached its maximum value. In a daisy chain of
AT17 Series devices, the CEO pin of one device must be connected to
the CE input of the next device in the chain. It will stay Low as long as
CE is low and OE is High. It will then follow CE until OE goes Low;
thereafter, CEO will stay High until the entire EEPROM is read again.
A2
I
Device selection input, A2. This is used to enable (or select) the device
during programming (i.e., when SER_EN is Low). A2 has an internal
pulldown resistor.
–
15
23
29
READY
(1)
O
Open collector reset state indicator. Driven Low during power-up reset,
released when power-up is complete. (Recommend a 4.7 k
pull-up on
this pin if used).
7
17
35
41
SER_EN
I
Serial enable must be held High during FPGA loading operations.
Bringing SER_EN Low enables the 2-wire Serial Programming Mode.
For non-ISP applications, SER_EN should be tied to V
CC
.
8
20
38
44
V
CC
+3.3V/+5V power supply pin.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17C002-10CC | FPGA Configuration EEPROM Memory |
| AT17C002-10CI | FPGA Configuration EEPROM Memory |
| AT17C002-10JC | FPGA Configuration EEPROM Memory |
| AT17C002-10JI | FPGA Configuration EEPROM Memory |
| AT17C002-10TQC | FPGA Configuration EEPROM Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17C002-10CC | 功能描述:FPGA-配置存儲器 ASICS RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17C002-10CI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17C002-10JC | 功能描述:FPGA-配置存儲器 ASICS RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17C002-10JI | 功能描述:FPGA-配置存儲器 ASICS RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17C002-10TQC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
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