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參數(shù)資料
| 型號： | AT17A |
| 廠商： | Atmel Corp. |
| 英文描述： | FPGA Configuration EEPROM |
| 中文描述： | FPGA配置的EEPROM |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 159K |
| 代理商： | AT17A |
AT17A Series
8
.
AC Characteristics for AT17C65/128A
V
CC
= 5V
±
5% Commercial / V
CC
= 5V
±
10% Ind./Mil.
.
AC Characteristics for AT17C128/256A When Cascading
V
CC
= 5V
±
5% Commercial / V
CC
= 5V
±
10% Ind./Mil.
Notes:
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pf.
3. Float delays are measured with 5 pF AC loads. Transition is measured
±
200 mV from steady-state active levels.
4. During cascade F
MAX
= 8 MHz.
Symbol
Description
Commercial
Industrial/Military
Units
Min
Max
Min
Max
t
OE
(2)
OE to Data Delay
110
150
ns
t
CE
(2)
CE to Data Delay
50
50
ns
t
CAC
(2)
CLK to Data Delay
50
55
ns
t
OH
(2)
Data Hold From CE, OE, or CLK
0
0
ns
t
DF
(3)
CE or OE to Data Float Delay
50
50
ns
t
LC
CLK Low Time
30
35
ns
t
HC
CLK High Time
30
35
ns
t
SCE
CE Setup Time to CLK (to guarantee proper counting)
45
50
ns
t
HCE
CE Hold Time to CLk (to guarantee proper counting)
0
5
ns
t
HOE
OE High Time (guarantees counter is reset)
50
60
ns
F
MAX
(4)
MAX Input Clock Frequency
10
10
MHz
Symbol
Description
Commercial
Industrial/Military
Units
Min
Max
Min
Max
t
CDF
(3)
CLK to Data Float Delay
50
50
ns
t
OCK
(2)
CLK to CEO Delay
65
75
ns
t
OCE
(2)
CE to CEO Delay
55
60
ns
t
OE
(2)
RESET/OE to CEO Delay
55
55
ns
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AT17C002 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
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| AT17C002-10BJI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17C002-10CC | 功能描述:FPGA-配置存儲器 ASICS RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17C002-10CI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
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