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參數(shù)資料
| 型號(hào)： | AT1362 |
| 廠商： | Aimtron Technology Corp. |
| 英文描述： | Synchronous Buck Converter With Power Good Detector & LDO |
| 中文描述： | 同步降壓轉(zhuǎn)換器的電源良好探測(cè)器 |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大?。?/td> | 709K |
| 代理商： | AT1362 |
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AT1362A/B
Preliminary Product Information
Synchronous Buck Converter
With Power Good Detector & LDO
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C.
Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW:
http://www.aimtron.com.tw
5/30/2006 REV:1.0 Email:
service@aimtron.com.tw
9
LDO
For general purposes, use a 2.2uF capacitor on the LDO output. Larger capacitor
values and lower ESR provide better supply noise rejection and transient response. A
higher value input capacitor may be necessary if large, fast transients are anticipated .
Ceramic capacitors have the lowest ESR, and will offer the best AC performance.
When choosing the input and output ceramic capacitors, choose the
X5R or X7R
dielectric formulations. These dielectrics have the best temperature and voltage
characteristics of all the ceramics for a given value and size.
Inductor Selection
The inductor is chosen based on the desired ripple current. Large value inductors
lower ripple current and small value inductors result in higher ripple current. Always
consider the losses associated with the DCR and its effect on the total converter
efficiency when selecting an inductor. The inductor is selected to limit the ripple
current to some predetermined value, typically 20~40% of the full load current at the
maximum input voltage. The formula of inductance value is as below:
)
(
4
~
2
MAX
OUT
L
I
I
×
=
×
=
IN
OUT
V
L
OUT
V
V
I
f
L
1
L
t
V
2
V
(
I
I
2
I
I
ON
OUT
×
IN
O
L
O
PK
×
+
=
+
=
)
Power Good Indicator with Adjustable Time Delay
When OUT1 pin is above 2.25V or 1.62V (typ.) and with a delay time (t1) the OUT2
is start to regulation. The PG pin terminal is an open drain output of N-MOS. Connect
a resistor from PG pin to VCC or OUT2 to create a logic signal. If OUT2 pin is less
than 2.97V (typ.) this pin is pulled to ground. When OUT2 pin is above 2.97V (typ.)
and with a delay time (t2) this pin is open. PG pin is forced low when in UVLO. The
formula of adjustable delay time is as below:
7
2
1
×
=
=
=
DELAY
I
V
C
t
t
time
delay
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT1362A | Synchronous Buck Converter With Power Good Detector & LDO |
| AT1362AN | Synchronous Buck Converter With Power Good Detector & LDO |
| AT1362B | Synchronous Buck Converter With Power Good Detector & LDO |
| AT1362BN | Synchronous Buck Converter With Power Good Detector & LDO |
| AT1366B | 1MHz,800mA Synchronous Buck Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT1362A | 制造商:AIMTRON 制造商全稱:AIMTRON 功能描述:Synchronous Buck Converter With Power Good Detector & LDO |
| AT1362AN | 制造商:AIMTRON 制造商全稱:AIMTRON 功能描述:Synchronous Buck Converter With Power Good Detector & LDO |
| AT1362B | 制造商:AIMTRON 制造商全稱:AIMTRON 功能描述:Synchronous Buck Converter With Power Good Detector & LDO |
| AT1362BN | 制造商:AIMTRON 制造商全稱:AIMTRON 功能描述:Synchronous Buck Converter With Power Good Detector & LDO |
| AT1366 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1MHZ 800MA SYNCHRONOUS BUCK CONTROLLER |
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