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參數(shù)資料
| 型號： | ASM813LESA-T |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 40=20X2 .004" SMD FEMALE HEADER |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | SOP-8 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 198K |
| 代理商： | ASM813LESA-T |
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Notice: The information in this document is subject to change without notice
Low Power μP Supervisor Circuits
ASM705 / 706 / 707 / 708
ASM813L
rev 1.5
February 2005
transitions at WDI will reset the watchdog timer and initiate a
new countdown sequence.
WDO will also become LOW and remain so, whenever the
supply voltage, V
CC
, falls below the device threshold level.
WDO goes HIGH as soon as V
CC
transitions above the
threshold. There is no minimum pulse width for WDO as
there is for the RESET outputs. If WDI is floated, WDO
essentially acts as a low-power output indicator.
Application Information
Ensuring That RESET is Valid Down to V
CC
= 0V
When V
CC
falls below 1.1V, the ASM705-708 RESET output
no longer pulls down; it becomes indeterminate. To avoid the
possibility that stray charges build up and force RESET to the
wrong state, a pull-down resistor should be connected to the
RESET pin, thus draining such charges to ground and
holding RESET low. The resistor value is not critical. A 100k
resistor will pull RESET to ground without loading it.
Bi-directional Reset Pin Interfacing
The ASM705/6/7/8 can interface with μP/μC bi-directional
reset pins by connecting a 4.7k
resistor in series with the
RESET output and the μP/μC bi-directional RESET pin.
Monitoring Voltages Other Than V
CC
The ASM705-708 can monitor voltages other than V
CC
using
the Power Fail circuitry. If a resistive divider is connected
from the voltage to be monitored to the Power Fail input
(PFI), the PFO will go LOW if the voltage at PFI goes below
1.25V reference. Should hysteresis be desired, connect a
resistor (equal to approximately 10 times the sum of the two
resistors in the divider) between the PFI and PFO pins. A
capacitor between PFI and GND will reduce circuit sensitivity
to input high-frequency noise. If it is desired to assert a
RESET for voltages other than V
CC
then the PFO output is to
be connected to the MR.
Supply Voltage
BUF
Buffered
RESET
V
CC
ASM70x
GND
GND
RESET
RESET
Input
μC or μP
4.7k
Bi-directional I/O Pin
Figure 3: Bi-directional Reset Pin Interfacing
V
CC
PFI
MR
PFO
V
IN
R
1
R
2
ASM70x
RESET
GND
+5V
To
μP
Figure 4: Monitoring +5V and an additional supply V
IN
WDI
WDO
RESET
RESET
Figure 2: Watchdog Timing
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