參數(shù)資料
型號(hào)： ASM812SEUS-T
廠商： ALLIANCE SEMICONDUCTOR CORP
元件分類： 電源管理
英文描述： 4 Pin P Voltage Supervisor with Manual Reset
中文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO4
封裝： PLASTIC, SOT-143, 4 PIN
文件頁(yè)數(shù)： 5/10頁(yè)
文件大?。?/td> 229K
代理商： ASM812SEUS-T
Reset Active Timeout Period
ASM811, ASM812
5 of 10
Notice: The information in this document is subject to change without notice
4 Pin μP Voltage Supervisor with Manual Reset
October 2003
rev 1.0
Electrical Characteristics:
Unless otherwise noted, V
CC
is over the full voltage range, T
A
= -40°C to 105°C.
Typical values at T
A
= 25°C, V
CC
= 5V for L/M/J devices, V
CC
= 3.3V for T/S devices and V
CC
= 3V for R devices.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
CC
Input Voltage Range
T
A
= 0°C to 70°C
T
A
= -40°C to 105°C
1.1
1.2
5.5
5.5
V
V
I
CC
Supply Current (Unloaded)
T
A
= -40°C to 85°C
T
A
= -40°C to 85°C
T
A
= 85°C to 105°C
T
A
= 85°C to 105°C
V
CC
< 5.5V, L/M/J
V
CC
< 3.6V, R/S/T
V
CC
< 5.5V, L/M/J
V
CC
< 3.6V, R/S/T
9
6.8
15
10
25
20
μA
V
TH
Reset Threshold
L devices
T
A
= 25°C
T
A
= -40°C to 85°C
T
A
= 85°C to 105°C
4.56
4.50
4.40
4.63
4.70
4.75
4.86
V
M devices
T
A
= 25°C
T
A
= -40°C to 85°C
T
A
= 85°C to 105°C
4.31
4.25
4.16
4.38
4.45
4.50
4.56
J devices
T
A
= 25°C
T
A
= -40°C to 85°C
T
A
= 85°C to 105°C
3.93
3.89
3.80
4.00
4.06
4.10
4.20
T devices
T
A
= 25°C
T
A
= -40°C to 85°C
T
A
= 85°C to 105°C
3.04
3.00
2.92
3.08
3.11
3.15
3.23
S devices
T
A
= 25°C
T
A
= -40°C to 85°C
T
A
= 85°C to 105°C
2.89
2.85
2.78
2.93
2.96
3.00
3.08
R devices
T
A
= 25°C
T
A
= -40°C to 85°C
T
A
= 85°C to 105°C
2.59
2.55
2.50
2.63
2.66
2.70
2.76
TC
VTH
Reset Threshold Temp.
Coefficient
30
ppm/°C
V
CC
to Reset Delay
V
CC
= V
TH
to (V
TH
- 125mV),
60
μs
T
A
= 0°C to 70°C
140
100
240
560
840
ms
T
A
= -40°C to 105°C
t
MR
MR Minimum Pulse Width
10
μs
Notes:
1. Production testing done at TA = 25°C. Over-temperature specifications guaranteed by design only using six sigma design limits.
2. RESET output is active LOW for the ASM811 and RESET output is active HIGH for the ASM812.
3. Glitches of 100ns or less typically will not generate a reset pulse.
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