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參數(shù)資料
| 型號： | ASM707EPA |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Low Power UP Supervisor Circuits |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 198K |
| 代理商： | ASM707EPA |
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Notice: The information in this document is subject to change without notice
Low Power μP Supervisor Circuits
ASM705 / 706 / 707 / 708
ASM813L
rev 1.5
February 2005
Detailed Description
A proper reset input enables a microprocessor /
microcontroller to start in a known state. ASM70X and
ASM813L assert reset to prevent code execution errors
during power-up, power-down and brown-out conditions.
RESET/RESET Timing
The RESET/RESET signals are designed to start a μP/μC in
a known state or return the system to a known state.
The ASM707/708 have two reset outputs, one active-HIGH
RESET and one active-LOW RESET output. The ASM813L
has only an active-HIGH output. RESET is simply the
complement of RESET.
RESET is guaranteed to be LOW with V
CC
above 1.2V.
During a power-up sequence, RESET remains low until the
supply rises above the threshold level, either 4.65V or 4.40V.
RESET goes high approximately 200ms after crossing the
threshold.
During power-down, RESET goes LOW as V
CC
falls below
the threshold level and is guaranteed to be under 0.4V with
V
CC
above 1.2V.
In a brownout situation where V
CC
falls below the threshold
level, RESET pulses low. If a brown-out occurs during an
already initiated reset, the pulse will continue for a minimum
of 140ms.
Power Failure Detection With Auxiliary Comparator
All devices have an auxiliary comparator with 1.25V trip point
and uncommitted output (PFO) and noninverting input (PFI).
This comparator can be used as a supply voltage monitor
with an external resistor voltage divider. The attenuated
voltage at PFI should be set just below the 1.25 threshold. As
the supply level falls, PFI is reduced causing the PFO output
to transit LOW. Normally PFO interrupts the processor so the
system can be shut down in a controlled manner.
Manual Reset (MR)
The active-LOW manual reset input is pulled high by a 250μA
pull-up current and can be driven low by CMOS/TTL logic or
a mechanical switch to ground. An external debounce circuit
is unnecessary since the 140ms minimum reset time will
debounce mechanical pushbutton switches.
By connecting the watchdog output (WDO) and MR, a
watchdog timeout forces RESET to be generated. The
ASM813L should be used when an active-HIGH RESET is
required.
Watchdog Timer
The watchdog timer available on the ASM705/706/813L
monitors μP/μC activity. An output line on the processor is
used to toggle the WDI line. If this line is not toggled within
1.6 seconds, the internal timer puts the watchdog output,
WDO, into a LOW state. WDO will remain LOW until a toggle
is detected at WDI.
If WDI is floated or connected to a three-stated circuit, the
watchdog function is disabled, meaning, it is cleared and not
counting. The watchdog timer is also disabled if RESET is
asserted. When RESET becomes inactive and the WDI input
sees a high or low transition as short as 50ns, the watchdog
timer will begin a 1.6 second countdown. Additional
Figure 1: WDI Three-state operation
5V
V
CC
RESET
MR
WDO
5V
5V
5V
0V
0V
0V
0V
MR externally
set low
t
MD
t
MR
t
RS
V
RT
t
RS
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| ASM707EPA-T | Low Power uP Supervisor Circuits |
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| ASM707ESA | CAP,100uF,20VDC,20-% Tol,20+% Tol |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM707EPAF | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Power uP Supervisor Circuits |
| ASM707EPAF-T | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Power uP Supervisor Circuits |
| ASM707EPA-T | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Power uP Supervisor Circuits |
| ASM707ESA | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Power uP Supervisor Circuits |
| ASM707ESAF | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:Low Power μP Supervisor Circuits |
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