參數(shù)資料
型號(hào): ASM706CUAF-T
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: Low Power uP Supervisor Circuits
中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
封裝: LEAD FREE, MICRO, SOP-8
文件頁(yè)數(shù): 3/16頁(yè)
文件大?。?/td> 274K
代理商: ASM706CUAF-T
ASM706 P/ R/ S/ T/ J
ASM708 R/ S/ T/ J
3 of 16
Notice: The information in this document is subject to change without notice
3/3.3/4.0 V μP Supervisor Circuits
October 2003
rev 1.0
Pin Description
Pin Number
Name
Function
ASM706P
ASM706R/S/T/J
ASM708R/S/T/J
DIP/
SO
MicroSO
DIP/
SO
MicroSO
DIP/
SO
MicroSO
1
3
1
3
1
3
MR
Manual reset input. The active LOW input triggers
a reset pulse. It is pulled HIGH by a 20k
pull-up
resistor. It is compatible with TTL/CMOS signals
when V
CC
= 5V. It can be shorted to ground
through a mechanical switch. Leave folating or
connect to V
CC
if the function is not used.
2
4
2
4
2
4
V
CC
Monitored power supply input.
3
5
3
5
3
5
GND
Ground.
4
6
4
6
4
6
PFI
Power-fail input voltage monitor. With PFI less
than 1.25V, PFO goes LOW. Connect PFI to
Ground when not in use.
5
7
5
7
5
7
PFO
Power-fail output. The output is active LOW and
sinks current when PFI is less than 1.25V. If not
used, leave the pin unconnected.
6
8
6
8
-
-
WDI
Watchdog input. WDI controls the internal watch-
dog timer. A HIGH or LOW signal for 1.6sec at
WDI allows the internal timer to run-out, setting
WDO low. A rising or falling edge must occur at
WDI within 1.6 seconds or WDO goes LOW. The
watchdog function is disabled by floating WDI. The
internal watchdog timer clears when: RESET is
asserted; WDI is three-stated ; or WDI sees a ris-
ing or falling edge.
-
-
-
-
6
8
NC
Not Connected
-
-
7
1
7
1
RESET
Active LOW reset output. Pulses LOW for 200ms
when triggered, and stays LOW whenever V
CC
is
below the reset threshold. RESET remains LOW
for 200ms after V
CC
rises above the reset thresh-
old or MR goes from HIGH to LOW. A watchdog
timeout will not trigger RESET unless WDO is con-
nected to MR.
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