- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381391 > ASM705CSAF-T (ALLIANCE SEMICONDUCTOR CORP) Low Power uP Supervisor Circuits PDF資料下載
參數(shù)資料
| 型號： | ASM705CSAF-T |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Low Power uP Supervisor Circuits |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | LEAD FREE, SOP-8 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 190K |
| 代理商： | ASM705CSAF-T |
ASM705 / 706 / 707 / 708
3 of 15
Notice: The information in this document is subject to change without notice
Low Power μP Supervisor Circuits
ASM813L
rev 1.2
July 2004
Pin Description
Pin Number
Name
Function
ASM705/706
ASM707/708
ASM813L
DIP/
SO
MicroSO
DIP/
SO
MicroSO
DIP/
SO
MicroSO
1
3
1
3
1
3
MR
Manual reset input. The active LOW input triggers a reset
pulse. A 250 μA pull-up current allows the pin to be
driven by TTL/CMOS logic or shorted to ground with a
switch.
2
4
2
4
2
4
V
CC
+5V power supply input.
3
5
3
5
3
5
GND
Ground reference for all signals.
4
6
4
6
4
6
PFI
Power-fail input voltage monitor. With PFI less than
1.25V, PFO goes LOW. Connect PFI to Ground or V
CC
when not in use.
5
7
5
7
5
7
PFO
Power-fail output. The output is active LOW and sinks
current when PFI is less than 1.25V.
6
8
-
-
6
8
WDI
Watchdog input. WDI controls the internal watchdog
timer. A HIGH or LOW signal for 1.6sec at WDI allows
the internal timer to run-out, setting WDO LOW. The
watchdog function is disabled by floating WDI or by con-
necting WDI to a high impedance three-state buffer. The
internal watchdog timer clears when: RESET is asserted;
WDI is three-stated ; or WDI sees a rising or falling edge.
-
-
6
8
-
-
NC
Not Connected
7
1
7
1
-
-
RESET
Active LOW reset output. Pulses LOW for 200ms when
triggered, and stays LOW whenever V
CC
is below the
reset threshold. RESET remains LOW for 200ms after
V
CC
rises above the reset threshold or MR goes from
LOW to HIGH. A watchdog timeout will not trigger
RESET unless WDO is connected to MR.
8
2
-
-
8
2
WDO
Watchdog output. WDO goes LOW when the 1.6 second
internal watchdog timer times-out and does not go HIGH
until the watchdog is cleared. In addition, when V
CC
falls
below the reset threshold, WDO goes LOW. Unlike
RESET, WDO does not have a minimum pulse width and
as soon as V
CC
exceeds the reset threshold, WDO goes
HIGH with no delay.
-
-
8
2
7
1
RESET
Active HIGH reset output. The inverse of RESET. The
ASM813L has only a RESET output.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM705EPA | Low Power UP Supervisor Circuits |
| ASM705EPA-T | Low Power uP Supervisor Circuits |
| ASM705EPAF | Low Power uP Supervisor Circuits |
| ASM705EPAF-T | Low Power uP Supervisor Circuits |
| ASM705ESA | Low Power UP Supervisor Circuits |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM705CSA-T | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Power uP Supervisor Circuits |
| ASM705CUA | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:Low Power μP Supervisor Circuits |
| ASM705CUAF | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Power uP Supervisor Circuits |
| ASM705CUAF-T | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Power uP Supervisor Circuits |
| ASM705CUA-T | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Power uP Supervisor Circuits |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。