參數(shù)資料
型號(hào): ASM5P23S05AF-1H-08-SR
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: 3.3V SpreadTrak Zero Delay Buffer
中文描述: 23S SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封裝: 0.150 INCH, LEAD FREE, SOIC-8
文件頁(yè)數(shù): 8/18頁(yè)
文件大?。?/td> 388K
代理商: ASM5P23S05AF-1H-08-SR
ASM5P23S09A
ASM5P23S05A
November 2004
rev 1.3
3.3V ‘preadTrak’Zero Delay Buffer
8 of 18
Notice: The information in this document is subject to change without notice.
Switching Characteristics for ASM5I23S05A-1H and ASM5I23S09A-1H Industrial Temperature Devices
7
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
1/t
1
Output Frequency
30 pF load
10 pF load
15
15
100
133
MHz
Duty Cycle
9
= (t
2
/ t
1
) * 100
Duty Cycle
9
= (t
2
/ t
1
) * 100
Output Rise Time
9
Output Fall Time
9
Output-to-output skew
9
Measured at 1.4 V, F
OUT
= 66.67 MHz
40.0
50.0
60.0
%
Measured at 1.4 V, F
OUT
< 50.0 MHz
45.0
50.0
55.0
t
3
Measured between 0.8V and 2.0V
1.50
nS
t
4
Measured between 2.0V and 0.8V
1.50
nS
t
5
All outputs equally loaded
250
pS
t
6
Delay, REF Rising Edge to
CLKOUT Rising Edge
9
Device-to-Device Skew
9
Measured at V
DD
/2
0
± 350
pS
t
7
Measured at V
DD
/2 on the CLKOUT
pins of the device
0
700
pS
t
8
Output Slew Rate
9
Measured between 0.8V and 2.0V
using Test Circuit #2
1
V/nS
t
J
Cycle-to-cycle jitter
9
Measured at 66.67 MHz, loaded
outputs
200
pS
t
LOCK
PLL Lock Time
9
Stable power supply, valid clock pre
sented on REF pin
1.0
mS
Note:
9. Parameter is guaranteed by design and characterization. Not 100% tested in production
相關(guān)PDF資料
PDF描述
ASM5I23S05AF-1H-08-SR PRECISION POT-7/8" 22MM DIA 3T WW RoHS Compliant: Yes
ASM5P23S05AF-1-08-SR 3.3V SpreadTrak Zero Delay Buffer
ASM5I23S05AF-1-08-SR 3.3V SpreadTrak Zero Delay Buffer
ASM5P23S05AF-1-08-ST 3.3V SpreadTrak Zero Delay Buffer
ASM5I23S05AF-1-08-ST 3.3V SpreadTrak Zero Delay Buffer
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