參數(shù)資料
型號(hào)： ASM5P2305A-1-08-ST
廠商： ALLIANCE SEMICONDUCTOR CORP
元件分類： 時(shí)鐘及定時(shí)
英文描述： 3.3V Zero Delay Buffer
中文描述： 2305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封裝： 0.150 INCH, SOIC-8
文件頁(yè)數(shù)： 1/20頁(yè)
文件大?。?/td> 398K
代理商： ASM5P2305A-1-08-ST
September 2005
rev 1.6
ASM5P2309A
ASM5P2305A
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
3.3V Zero Delay Buffer
General Features
15MHz to 133MHz operating range, compatible
with CPU and PCI bus frequencies.
Zero input - output propagation delay.
Multiple low-skew outputs.
Output-output skew less than 250pS.
Device-device skew less than 700pS.
One input drives 9 outputs, grouped as
4 + 4 + 1(ASM5P2309A).
One input drives 5 outputs (ASM5P2305A).
Less than 200 pS cycle-to-cycle jitter is compatible
with Pentium
based systems.
Test Mode to bypass PLL (ASM5P2309A only,
Refer Select Input Decoding Table).
Available in 16pin 150-mil SOIC, 4.4 mm TSSOP
(ASM5P2309A), and in 8pin 150-mil SOIC
package (ASM5P2305A).
3.3V operation, advanced 0.35μ CMOS
technology.
Functional Description
ASM5P2309A is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks. It accepts one
reference input and drives out nine low-skew clocks. It is
available in a 16-pin package. The ASM5P2305A is the
eight-pin version of the ASM5P2309A. It accepts one
reference input and drives out five low-skew clocks.
The -1H version of the ASM5P23XXA operates at up to
Block Diagram
133MHz frequencies, and has higher drive than the -1
devices. All parts have on-chip PLLs that lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
The ASM5P2309A has two banks of four outputs each,
which can be controlled by the Select inputs as shown in
the Select Input Decoding Table. The select input also
allows the input clock to be directly applied to the outputs
for chip and system testing purposes.
Multiple ASM5P2309A and ASM5P2305A devices can
accept the same input clock and distribute it. In this case
the skew between the outputs of the two devices is
guaranteed to be less than 700pS.
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 350pS, and the output to output skew is
guaranteed to be less than 250pS.
The ASM5P2309A and the ASM5P2305A are available in
two different configurations, as shown in the ordering
information table. The ASM5P2305A-1/ ASM5P2309A-1 is
the base part. The ASM5P2305A-1H/ ASM5P2309A-1H is
the high drive version of the -1 and its rise and fall times
are much faster than -1 part.
ASM5P2309A
PLL
MUX
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Select Input
Decoding
S2
S1
REF
PLL
CLKOUT
CLK1
CLK2
CLK3
CLK4
ASM5P2305A
REF
相關(guān)PDF資料
PDF描述
ASM5I2305A-1-08-ST 3.3V Zero Delay Buffer
ASM5P2305A-1-08-TR BEAD CORE DUAL 3.5X5MM RAD T/B
ASM5I2305A-1-08-TR BEAD CORE SINGLE 3.5X5MM AXIAL
ASM5P2305A-1-08-TT BEAD CORE SNGL 3.5X5MM AXIAL T/B
ASM5I2305A-1-08-TT 3.3V Zero Delay Buffer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ASM5P2305A-1-08-TR 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V Zero Delay Buffer
ASM5P2305A-1-08-TT 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V Zero Delay Buffer
ASM5P2305A-1H-08-SR 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V Zero Delay Buffer
ASM5P2305A-1H-08-ST 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V Zero Delay Buffer
ASM5P2305A-1H-08-TR 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V Zero Delay Buffer
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