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參數(shù)資料
| 型號： | ASM5I9775AG-52-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| 中文描述： | 9775 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 1 MM HEIGHT, GREEN, TQFP-52 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 507K |
| 代理商： | ASM5I9775AG-52-ET |
June 2005
ASM5I9775A
rev 0.3
Pin Description
1
2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer
3 of 12
Notice: The information in this document is subject to change without notice.
Pin
Name
I/O
Type
Description
9
TCLK0
I, PD
LVCMOS
LVCMOS/LVTTL reference clock input
10
TCLK1
I, PU
LVCMOS
LVCMOS/LVTTL reference clock input
16, 18,
21, 23,
25
32, 34,
36, 38,
40
44, 46,
48, 50
QA(4:0)
O
LVCMOS
Clock output bank A
QB(4:0)
O
LVCMOS
Clock output bank B
QC(3:0)
O
LVCMOS
Clock output bank C
29
FB_OUT
O
LVCMOS
Feedback clock output
. Connect to FB_IN for normal operation.
31
FB_IN
I, PU
LVCMOS
Feedback clock input
. Connect to FB_OUT for normal operation.
This input should be at the same voltage rail as input reference
clock. See
Table 1
.
2
MR#/OE
I, PU
LVCMOS
Output enable/disable input
. See
Table 2
.
3
CLK_STP#
I, PU
LVCMOS
Clock stop enable/disable input
. See
Table 2
.
6
PLL_EN
I, PU
LVCMOS
PLL enable/disable input
. See
Table 2
.
8
TCLK_SEL
I, PD
LVCMOS
Reference select input
. See
Table 2
.
11, 52
VCO_SEL(1,0)
I, PD
LVCMOS
VCO divider select input
. See
Tables 2, 3 and 4.
7, 4, 5
SEL(A:C)
I, PD
LVCMOS
Frequency select input, Bank (A:C)
. See
Table 3
.
20, 14
17, 22,
26
33, 37,
41
45, 49
FB_SEL(1,0)
I, PD
LVCMOS
Feedback dividers select inputs
. See
Table 4
.
VDDQA
Supply
VDD
2.5V or 3.3V Power supply for bank A output clocks
2,3
VDDQB
Supply
VDD
2.5V or 3.3V Power supply for bank B output clocks
2,3
VDDQC
Supply
VDD
2.5V or 3.3V Power supply for bank C output clocks
2,3
28
Supply
VDD
2.5V or 3.3V Power supply for feedback output clock
2,3
13
AVDD
Supply
VDD
2.5V or 3.3V Power supply for PLL
2,3
12
VDD
Supply
VDD
2.5V or 3.3V Power supply for core and inputs
2,3
15
AVSS
Supply
Ground
Analog Ground
1, 19,
24, 30,
35, 39,
43, 47,
51
27, 42
VSS
Supply
Ground
Common Ground
NC
No Connection
Notes:
1. PU = Internal pull-up, PD = Internal pull-down
2. A 0.1μF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power
supply pins.
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| ASM5P2304A | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
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| ASM5P2304A-1-08-ST | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V Zero Delay Buffer |
| ASM5P2304A-1H-08-SR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V Zero Delay Buffer |
| ASM5P2304A-1H-08-ST | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V Zero Delay Buffer |
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