- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381377 > ASM5I9774AG-52-ER (ALLIANCE SEMICONDUCTOR CORP) 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer PDF資料下載
參數(shù)資料
| 型號： | ASM5I9774AG-52-ER |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| 中文描述： | 9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 1 MM HEIGHT, GREEN, TQFP-52 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 477K |
| 代理商： | ASM5I9774AG-52-ER |
June 2005
rev 0.3
AC Electrical Specifications
(VDD
= 3.3V ± 5%, T
A
= –40°C to +85°C)
1
Parameter
Description
ASM5I9774A
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
8 of 12
Notice: The information in this document is subject to change without notice.
Condition
Min
Typ
Max
Unit
f
VCO
f
in
VCO Frequency
Input Frequency
200
-
500
MHz
÷8 Feedback
25
-
62.5
÷12 Feedback
16.6
-
41.6
÷16 Feedback
12.5
-
31.25
÷24 Feedback
8.3
-
20.8
÷32 Feedback
6.25
-
15.625
÷48 Feedback
Bypass mode
(PLL_EN = 0)
4.2
-
10.4
0
-
200
MHz
f
refDC
Input Duty Cycle
25
-
75
%
t
r
, t
f
f
MAX
TCLK Input Rise/FallTime
Maximum Output Frequency
0.8V to 2.0V
-
1.0
nS
÷4 Output
50
-
125
÷8 Output
25
-
62.5
÷12 Output
16.6
-
41.6
÷16 Output
12.5
-
31.25
÷24 Output
8.3
-
20.8
MHz
DC
Output Duty Cycle
45
-
55
%
t
r
, t
f
t
(
φ
)
Output Rise/Fall times
0.8V to 2.4V
0.1
1.0
nS
Propagation Delay (static phase
offset)
TCLK to FB_IN, same
VDD, does not include jitter
–100
-
100
pS
t
sk(O)
t
sk(B)
Output-to-Output Skew
Bank-to-Bank Skew
Skew within Bank
-
-
150
pS
Banks at same voltage,
same frequency
-
-
150
Banks at same voltage,
different frequency
-
-
225
Banks at different voltage
-
-
250
pS
t
PLZ, HZ
Output Disable Time
-
-
10
nS
t
PZL, ZH
BW
Output Enable Time
-
-
10
nS
PLL Closed Loop Bandwidth
(–3dB)
Cycle-to-Cycle Jitter
-
0.5 - 1.0
-
MHz
Same frequency
-
-
150
t
JIT(CC)
Multiple frequencies
-
-
300
pS
t
JIT(PER)
Period Jitter
-
-
100
pS
t
JIT(
φ
)
I/O Phase Jitter
I/O at same VDD
-
-
150
pS
t
LOCK
Maximum PLL Lock Time
-
-
1
mS
Note: 1. AC characteristics apply for parallel output termination of 50
to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are
guaranteed by characterization and are not 100% tested.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9774AG-52-ET | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A | Octal D-Type Flip-Flops With Clear 20-SO -40 to 85 |
| ASM5I9774A-52-ER | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5I9774A-52-ET | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5I9775A | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9774AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9775A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
| ASM5I9775A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
| ASM5I9775A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
| ASM5I9775AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。