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參數(shù)資料
| 型號(hào)： | ASM5I961P |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | Low Voltage Zero Delay Buffer |
| 中文描述： | 低壓零延遲緩沖器 |
| 文件頁(yè)數(shù)： | 1/14頁(yè) |
| 文件大小： | 625K |
| 代理商： | ASM5I961P |
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July 2005
rev 0.2
ASM5I961P
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
Low Voltage Zero Delay Buffer
Features
Fully Integrated PLL
Up to 200MHz I/O Frequency
LVCMOS Outputs
Outputs Disable in High Impedance
LVPECL Reference Clock Options
LQFP Packaging
±50pS Cycle–Cycle Jitter
150pS Output Skews
Functional Description
The ASM5I961P is a 2.5V or 3.3V compatible, 1:18 PLL
based zero delay buffer. With output frequencies of up to
200MHz, output skews of 150pS the device meets the
needs of the most demanding clock tree applications.
The ASM5I961P is offered with two different input
configurations. The ASM5I961P offers an LVCMOS
Block Diagram
reference clock while the ASM5I961P offers an LVPECL
reference clock.
When pulled high the OE pin will force all of the outputs
(except QFB) into a high impedance state. Because the OE
pin does not affect the QFB output, down stream clocks
can be disabled without the internal PLL losing lock.
The ASM5I961P is fully 2.5V or 3.3V compatible and
requires no external loop filter components. All control
inputs accept LVCMOS compatible levels and the outputs
provide low impedance LVCMOS outputs capable of
driving terminated 50
transmission lines. For series
terminated lines the ASM5I961P can drive two lines per
output giving the device an effective fanout of 1:36. The
device is packaged in a 32 lead LQFP package to provide
the
optimum
combination
of
board
density
and
performance.
Figure 1. ASM5I961P Logic Diagram
PCLK
PCLK
Q0
Q1
Q2
Q3
Q14
Q15
Q16
QFB
0
1
100-200 MHz
50-100 MHz
Ref
FB
PLL
50K
50K
50K
50K
FB_IN
F_RANGE
OE
50K
V
CC
50K
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I961P-32LR | Low Voltage Zero Delay Buffer |
| ASM5I9653A-32-ER | 3.3V 1:8 LVCMOS PLL Clock Generator |
| ASM5I9653A-32-LR | 3.3V 1:8 LVCMOS PLL Clock Generator |
| ASM5I9653A | 3.3V 1:8 LVCMOS PLL Clock Generator |
| ASM5I9653AG-32-ER | 3.3V 1:8 LVCMOS PLL Clock Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I961P-32LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961PG-32LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I9653A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1:8 LVCMOS PLL Clock Generator |
| ASM5I9653A-32-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1:8 LVCMOS PLL Clock Generator |
| ASM5I9653A-32-LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1:8 LVCMOS PLL Clock Generator |
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