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參數(shù)資料
| 型號： | ASM5I9351-32-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| 中文描述： | 9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 1 MM HEIGHT, TQFP-32 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大小： | 522K |
| 代理商： | ASM5I9351-32-ET |
July 2005
rev 0.2
ASM5I9351
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
6 of 13
Notice: The information in this document is subject to change without notice.
AC Electrical Specifications
(V
DD
= 2.5V ± 5%, T
A
= -40°C to +85°C)
1
Parameter
f
VCO
Description
Condition
Min
200
Typ
-
Max
380
Unit
MHz
VCO Frequency
÷2 Feedback
100
-
190
÷4 Feedback
50
-
95
÷8 Feedback
25
-
47.5
f
in
Input Frequency
Bypass mode (PLL_EN = 0)
0
-
200
MHz
f
refDC
V
PP
V
CMR
t
r
, t
f
Input Duty Cycle
25
-
75
%
Peak-Peak Input Voltage
Common Mode Range
2
LVPECL
500
-
1000
mV
LVPECL
1.2
-
VDD– 0.6
V
TCLK Input Rise/FallTime
0.7V to 1.7V
-
-
1.0
nS
÷2 Output
100
-
190
÷4 Output
50
-
95
f
MAX
Maximum Output Frequency
÷8 Output
25
-
47.5
MHz
f
MAX
< 100 MHz
f
MAX
> 100 MHz
0.6V to 1.8V
47.5
-
52.5
DC
Output Duty Cycle
45
-
55
%
t
r
, t
f
Output Rise/Fall times
0.1
-
1.0
nS
TCLK to FB_IN
–100
-
100
t
(
φ
)
Propagation Delay
(static phase offset)
PCLK to FB_IN
–100
-
100
pS
t
sk(O)
t
PLZ, HZ
t
PZL, ZH
Output-to-Output Skew
-
-
150
pS
Output Disable Time
-
-
10
nS
Output Enable Time
-
-
10
nS
÷2 Feedback
-
2.2
-
÷4 Feedback
-
0.85
-
BW
PLL Closed Loop Bandwidth
(–3dB)
÷8 Feedback
-
0.6
-
MHz
Same frequency
-
-
150
t
JIT(CC)
Cycle-to-Cycle Jitter
Multiple frequencies
-
-
250
pS
Same frequency
-
-
100
t
JIT(PER)
Period Jitter
Multiple frequencies
-
-
175
pS
t
JIT(
φ
)
t
LOCK
Note: 1
AC characteristics apply for parallel output termination of 50
to V
TT
. Parameters are guaranteed by characterization and are not 100% tested.
2. V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
range and the input
swing lies within the V
PP
(AC) specification. Violation of V
CMR
or V
PP
impacts static phase offset t(
φ
).
I/O Phase Jitter
-
175
-
pS
Maximum PLL Lock Time
-
-
1
mS
相關PDF資料 |
PDF描述 |
|---|---|
| ASM5I9351-32-LT | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9352G-32-ET | CONNECTOR ACCESSORY |
| ASM5I9352G-32-LT | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352 | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352-32-ET | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9351-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351G-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351G-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9352 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
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