參數(shù)資料
型號(hào): ASM5I2308A-4-16-ST
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: 時(shí)鐘及定時(shí)
英文描述: 3.3V Zero-Delay Buffer
中文描述: 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝: 0.150 INCH, SOIC-16
文件頁數(shù): 6/18頁
文件大?。?/td> 387K
代理商: ASM5I2308A-4-16-ST
September 2005
rev 1.4
Switching Characteristics for ASM5P2308A Commercial Temperature Devices
ASM5P2308A
3.3V Zero Delay Buffer
6 of 18
Notice: The information in this document is subject to change without notice.
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
1/t
1
Output Frequency
30pF load, All devices
15
100
MHz
1/t
1
Output Frequency
15pF load, -1H, -5H devices
8
15
133
MHz
t
1/
Output Frequency
15pF load, -1, -2, -3, -4 devices
15
133
MHz
Duty Cycle
9
= (t
2
/ t
1
) * 100
(-1, -2, -3, -4, -1H, -5H)
Measured at 1.4V, F
OUT
= <66.66MHz
30pF load
40.0
50.0
60.0
%
Duty Cycle
9
= (t
2
/ t
1
) * 100
(-1, -2, -3, -4, -1H, -5H)
Measured at 1.4V, F
OUT
= <50MHz
15pF load
45.0
50.0
55.0
%
t
3
Output Rise Time
9
(-1, -2, -3, -4)
Measured between 0.8V and 2.0V 30pF load
2.20
nS
t
3
Output Rise Time
9
(-1, -2, -3, -4)
Measured between 0.8V and 2.0V 15pF load
1.50
nS
t
3
Output Rise Time
9
(-1H, -5H)
Measured between 0.8V and 2.0V 30pF load
1.50
nS
t
4
Output Fall Time
9
(-1, -2, -3, -4)
Measured between 2.0V and 0.8V 30pF load
2.20
nS
t
4
Output Fall Time
9
(-1, -2, -3, -4)
Measured between 0.8V and 2.0V 15pF load
1.50
nS
t
4
Output Fall Time
9
(-1H, -5H)
Measured between 2.0V and 0.8V 30pF load
1.25
nS
Output-to-output skew on same
bank (-1, -2, -3, -4)
9
All outputs equally loaded
200
pS
Output-to-output skew
(-1H, -5H)
All outputs equally loaded
200
Output bank A -to- output
Bank B skew (-1, -4, -5H)
All outputs equally loaded
200
t
5
Output bank A -to- output
Bank B skew (-2, -3)
All outputs equally loaded
400
t
6
Delay, REF Rising Edge to FBK
Rising Edge
9
Measured at V
DD
/2
0
±250
pS
t
7
Device-to-Device Skew
9
Measured at V
DD
/2 on the FBK pins of the device
0
700
pS
Measured at 66.67MHz, loaded outputs, 15pF load
200
pS
Measured at 66.67MHz, loaded outputs, 30pF load
200
t
J
Cycle-to-cycle jitter
9
(-1, -1H, -4, -5H)
Measured at 133.3MHz, loaded outputs, 15pF load
100
Measured at 66.67MHz, loaded outputs, 30pF load
400
pS
t
J
Cycle-to-cycle jitter
9
(-2, -3)
Measured at 66.67MHz, loaded outputs, 15pF load
400
t
LOCK
PLL Lock Time
9
Stable power supply, valid clock presented on REF
and FBK pins
1.0
mS
Note:
9. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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