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參數(shù)資料
| 型號(hào)： | ASM5I2304AF-1H-08-ST |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3 V Zero Delay Buffer |
| 中文描述： | 2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, SOIC-8 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 300K |
| 代理商： | ASM5I2304AF-1H-08-ST |
September 2005
rev 1.4
ASM5P2304A
Notice: The information in this document is subject to change without notice.
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
3.3V Zero Delay Buffer
Features
Zero input - output propagation delay, adjustable
by capacitive load on FBK input.
Multiple configurations - Refer “ASM5P2304A
Configurations Table”
Input frequency range: 15MHz to 133MHz
Multiple low-skew outputs.
Output-output skew less than 200pS.
Device-device skew less than 500pS.
Two banks of four outputs.
Less than 200pS Cycle-to-Cycle jitter
(-1, -1H, -2, -2H).
Available in space saving, 8 pin 150-mil SOIC
packages.
3.3V operation.
Advanced 0.35
μ
CMOS technology.
Industrial temperature available.
Functional Description
ASM5P2304A is a versatile, 3.3V zero-delay buffer
designed
to
distribute
high-speed
workstation, datacom, telecom and other high-performance
applications. It is available in 8 pin package. The part has
an on-chip PLL which locks to an input clock presented on
clocks
in
PC,
the REF pin. The PLL feedback is required to be driven to
FBK pin, and can be obtained from one of the outputs. The
input-to-output propagation delay is guaranteed to be less
than 250pS, and the output-to-output skew is guaranteed to
be less than 200pS.
The ASM5P2304A has two banks of two outputs each.
Multiple ASM5P2304A devices can accept the same input
clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than
500pS.
The
ASM5P2304A
is
available
configurations (Refer “ASM5P2304A Configurations Table).
The ASM5P2304A-1 is the base part, where the output
frequencies equal the reference if there is no counter in the
feedback path. The ASM5P2304A-1H is the high-drive
version of the -1 and the rise and fall times on this device
are much faster.
The ASM5P2304A-2 allows the user to obtain REF and
1/2X or 2X frequencies on each output bank. The exact
configuration and output frequencies depend on which
output drives the feedback pin.
in
two
different
Block Diagram
PLL
/2
Extra Divider (-2)
CLKA2
CLKA1
FBK
CLKB1
CLKB2
REF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I2304AF-2-08-SR | 3.3 V Zero Delay Buffer |
| ASM5I2304AF-2-08-ST | 3.3 V Zero Delay Buffer |
| ASM5I2304AG-1H-08-ST | 3.3 V Zero Delay Buffer |
| ASM5I2304AG-2-08-SR | 3.3 V Zero Delay Buffer |
| ASM5I2304AG-2-08-ST | 3.3 V Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I2304AF-2-08-SR | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
| ASM5I2304AF-2-08-ST | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
| ASM5I2304AF-2H-08-SR | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
| ASM5I2304AF-2H-08-ST | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
| ASM5I2304AG-1-08-SR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V Zero Delay Buffer |
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