參數(shù)資料
型號: ASM3P623S00FF-16-TT
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: 時鐘及定時
英文描述: Zero Cycle Slip Peak EMI reduction IC
中文描述: 3P SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝: 4.40 MM, ROHS COMPLIANT, TSSOP-16
文件頁數(shù): 3/16頁
文件大?。?/td> 301K
代理商: ASM3P623S00FF-16-TT
July 2005
rev 1.0
Pin Description for ASM3P623S00A/B/C
ASM3P623S00A/B/C/D/E/F
Zero Cycle Slip Peak EMI Reduction IC
3 of 16
Notice: The information in this document is subject to change without notice.
Pin #
Pin Name
Description
1
CLKIN
2
Input reference frequency, 5V-tolerant input
2
NC
SS%
4
No Connect
3
Spread Spectrum Selection
4
GND
SSON
4
Ground
5
Spread Spectrum enable and disable option When SSON is HIGH, the spread
spectrum is enabled and when LOW, it turns off the spread spectrum.
6
CLKOUT
1,3
Buffered clock output
7
VDD
3.3V supply
8
NC
No Connect
Pin Description for ASM3P623S00D/E/F
Pin #
Pin Name
Description
1
CLKIN
2
CLKOUT1
3
Input reference frequency, 5V tolerant input
2
Buffered clock output
3
VDD
SS%
4
3.3V supply
4
Spread Spectrum Selection
5
GND
Ground
6
CLKOUT2
3
CLKOUT3
3
Buffered clock output
7
Buffered clock output
8
DLY CNTRL
The pin is used to skew the outputs such that they align with the input. The skew can
is in the range of 100-200pS
9
SSON
4
Spread Spectrum enable and disable option. When SSON is HIGH, the spread
spectrum is enabled and when LOW, it turns off the spread spectrum.
10
CLKOUT4
3
CLKOUT5
3
Buffered clock output
11
Buffered clock output
12
GND
Ground
13
VDD
3.3V supply
14
CLKOUT6
3
CLKOUT7
3
CLKOUT8
3
Buffered clock output
15
Buffered clock output
16
Buffered clock output
Notes:
1. This output is driven and has an internal feedback for the PLL.
2. Weak pull-down. 3. Weak pull-down on all outputs. 4. Weak pull-up on these inputs.
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