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參數(shù)資料
| 型號： | ASM3I623S00EG-16-ST |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PWR SPLY EXT MED 10W 9V @ 1.1A |
| 中文描述： | 3I SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 301K |
| 代理商： | ASM3I623S00EG-16-ST |
July 2005
rev 1.0
ASM3P623S00A/B/C/D/E/F
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
Zero Cycle Slip Peak EMI reduction IC
General Features
Input frequency range: 20MHz - 50MHz.
Zero input - output propagation delay.
Low-skew outputs.
Output-output skew less than 250pS.
Device-device skew less than 700pS.
Less than 200pS cycle-to-cycle jitter is compatible
with Pentium
based systems.
Available in 16pin, 150mil SOIC, 4.4mm TSSOP
(ASM3P623S00D/E/F), and in 8pin, 150 mil SOIC,
4.4mm TSSOP Packages (ASM3P623S00A/B/C).
3.3V operation
Advanced 0.35μ CMOS technology.
The First True Drop-in Solution.
Functional Description
ASM3P623S00D/E/F is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks. It accepts one
reference input and drives out eight low-skew clocks. It is
available in a 16pin package. The ASM3P623S00A/B/C is
the eight-pin version of the ASM3P623S00. It accepts one
reference input and drives out one low-skew clock.
Block Diagram
All parts have on-chip PLLs that lock to an input clock on
the CLKIN pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad, internal to the device.
Multiple ASM3P623S00D/E/F devices can accept the same
input clock and distribute it. In this case, the skew between
the outputs of the two devices is guaranteed to be less than
700pS.
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 250pS, and the output-to-output skew is
guaranteed to be less than 250pS.
Please refer
“
Differential Cycle Slips and Spread Spectrum
Control Table” for deviations and differential Cycle Slips
for ASM3P623S00A/B/C and the ASM3P623S00D/E/F
devices
The ASM3P623S00A/B/C and the ASM3P623S00D/E/F
are available in two different configurations, as shown in
the ordering information table.
V
SS
CLKIN
Reference
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
VCO
Feedforward
Divider
PLL
V
DD
CLKOUT
SSON
SS%
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| ASM3P623S00EG-16-TT | Zero Cycle Slip Peak EMI reduction IC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM3I623S00EG-16-TR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Zero Cycle Slip Peak EMI reduction IC |
| ASM3I623S00EG-16-TT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Zero Cycle Slip Peak EMI reduction IC |
| ASM3I623S00FF-16-SR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Zero Cycle Slip Peak EMI reduction IC |
| ASM3I623S00FF-16-ST | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Zero Cycle Slip Peak EMI reduction IC |
| ASM3I623S00FF-16-TR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Zero Cycle Slip Peak EMI reduction IC |
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