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參數(shù)資料
| 型號： | ASM3I623S00CF-08-TR |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Zero Cycle Slip Peak EMI reduction IC |
| 中文描述： | 3I SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, SOIC-8 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 301K |
| 代理商： | ASM3I623S00CF-08-TR |
July 2005
rev 1.0
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the
edge rates also get faster. Analysis shows that a square
wave is composed of fundamental frequency and
harmonics. The fundamental frequency and harmonics
generate the energy peaks that become the source of
EMI. Regulatory agencies test electronic equipment by
measuring the amount of peak energy radiated from the
equipment. In fact, the peak level allowed decreases as
the frequency increases. The standard methods of
reducing EMI are to use shielding, filtering, multi-layer
Cycle Slip
Cycle slip occurs when the output clock edge
‘wanders’ away from the corresponding input clock
edge. There are two types of cycle slips – a Differential
cycle slip and an Integral cycle slip. The differential
cycle slip is caused due the clock edge variation over
one modulation cycle. It is defined by the maximum
amount of ‘wander’ the clock edge will have within one
Pin Configuration
ASM3P623S00A/B/C/D/E/F
Zero Cycle Slip Peak EMI Reduction IC
2 of 16
Notice: The information in this document is subject to change without notice.
PCBs etc. These methods are expensive. Spread
spectrum clocking reduces the peak energy by reducing
the Q factor of the clock. This is done by slowly
modulating the clock frequency. The ASM3P623S00X
uses the center modulation spread spectrum technique in
which the modulated output frequency varies above and
below the reference frequency with a specified
modulation rate. With center modulation, the average
frequency is the same as the unmodulated frequency and
there is no performance degradation
modulation cycle. Integral cycle slip occurs due to the
accumulation of the cycle slip over successive modulation
cycles. In ASM3P623S00A/B/C/D/E/F the differential cycle
slip is within the value mentioned in the
“
Differential Cycle
Slip and Spread Spectrum Control Table” and the Integral
Cycle Slip is ‘Zero’.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLKIN
CLKOUT1
VDD
CLKOUT6
CLKOUT7
CLKOUT4
CLKOUT5
GND
VDD
GND
CLKOUT8
SS%
ASM3P623S00 D/E/F
CLKOUT2
CLKOUT3
DLY CNTRL
SSON
1
2
3
4
5
6
7
8
CLKIN
NC
SS%
GND
V
DD
SSON
CLKOUT
NC
ASM3P623S00A/B/C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM3P623S00CF-08-TT | Zero Cycle Slip Peak EMI reduction IC |
| ASM3I623S00CF-08-TT | Zero Cycle Slip Peak EMI reduction IC |
| ASM3P623S00DG-16-SR | Zero Cycle Slip Peak EMI reduction IC |
| ASM3I623S00DG-16-SR | Zero Cycle Slip Peak EMI reduction IC |
| ASM3P623S00DG-16-ST | Zero Cycle Slip Peak EMI reduction IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM3I623S00CF-08-TT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Zero Cycle Slip Peak EMI reduction IC |
| ASM3I623S00CG-08-SR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Zero Cycle Slip Peak EMI reduction IC |
| ASM3I623S00CG-08-ST | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Zero Cycle Slip Peak EMI reduction IC |
| ASM3I623S00CG-08-TR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Zero Cycle Slip Peak EMI reduction IC |
| ASM3I623S00CG-08-TT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Zero Cycle Slip Peak EMI reduction IC |
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