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參數(shù)資料
| 型號： | ASM2P3805AHG-20-ST |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LJT 6C 6#22M SKT RECP |
| 中文描述： | 3805 SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | 0.300 INCH, GREEN, SOIC-20 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 534K |
| 代理商： | ASM2P3805AHG-20-ST |
June 2005
rev 0.2
ASM2P3805AH
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
3.3V CMOS Buffer Clock Driver
Features
Advanced CMOS Technology
Guaranteed low skew < 500pS (max.)
Very low duty cycle distortion < 1.0nS (max)
Very low CMOS power levels
TTL compatible inputs and outputs
Inputs can be driven from 3.3V or 5V components
Two independent output banks with 3-state control
1:5 fanout per bank
"Heartbeat" monitor output
V
CC
= 3.3V ± 0.3V
Available in SSOP, SOIC and QSOP Packages
Block Diagram
Functional Description
The ASM2P3805AH is a 3.3V, non-inverting clock driver
built using advanced CMOS technology. The device
consists of two banks of drivers, each with a 1:5 fanout and
its own output enable control. The device has a "heartbeat"
monitor for diagnostics and PLL driving. The MON output is
identical to all other outputs and complies with the output
specifications in this document. The ASM2P3805AH offers
low capacitance inputs.
The ASM2P3805AH is designed for high speed clock
distribution where signal quality and skew are critical. The
ASM2P3805AH
also
allows
transmission line driving in applications such as address
distribution, where one signal must be distributed to
multiple receivers with low skew and high signal quality.
Pin Diagram
V
CCA
1 20
single
point-to-point
IN
A
IN
B
OE
B
OE
A
OA
1
– OA
5
OB
1
– OB
5
MON
5
5
V
CCB
OB
1
OB
2
OB
3
GND
B
OB
4
OB
5
MON
OE
B
IN
B
IN
A
OE
A
GND
Q
OA
5
OA
4
GND
A
OA
3
OA
2
OA
1
A
A
10 11
9 12
8 13
7 14
6 15
5 16
4 17
3 18
2 19
相關PDF資料 |
PDF描述 |
|---|---|
| ASM2I3805AG-20-AR | 3.3V CMOS Buffer Clock Driver |
| ASM2I3805AG-20-AT | 3.3V CMOS Buffer Clock Driver |
| ASM2I3805AG-20-DR | 3.3V CMOS Buffer Clock Driver |
| ASM2I3805AG-20-DT | 3.3V CMOS Buffer Clock Driver |
| ASM2I3805AG-20-SR | 3.3V CMOS Buffer Clock Driver |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ASM2P3805DG-20-AR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V CMOS Dual 1-To-5 Clock Driver |
| ASM2P3805DG-20-AT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V CMOS Dual 1-To-5 Clock Driver |
| ASM2P3805DG-20-DR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V CMOS Dual 1-To-5 Clock Driver |
| ASM2P3805DG-20-DT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V CMOS Dual 1-To-5 Clock Driver |
| ASM2P3805EG-20-AR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V CMOS Dual 1-To-5 Clock Driver |
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