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參數(shù)資料
| 型號： | ASM2P20805A-20-AR |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 2.5V CMOS Dual 1-To-5 Clock Driver |
| 中文描述： | 20805 SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | 0.150 INCH, SSOP-20 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 486K |
| 代理商： | ASM2P20805A-20-AR |
June 2005
rev 0.2
Switching Characteristics Over Operating Range
3,4
ASM2P20805A
2.5V CMOS Dual 1-To-5 Clock Driver
5 of 11
Notice: The information in this document is subject to change without notice.
Symbol
Parameter
Conditions
1
Min
2
Max
Unit
t
PLH
t
PHL
Propagation Delay
IN
A
to OA
n
, IN
B
to OB
n
1
3
nS
t
R
Output Rise Time
(Measured from 0.8V to 2V)
-
1.5
nS
t
F
Output Fall Time
(Measured from 2V to 0.8V)
-
1.5
nS
t
SK(O)
Same device output pin to pin skew
5
-
270
pS
t
SK(P)
Pulse skew
6,9
-
270
pS
t
SK(PP)
Part to part skew
7
-
550
pS
t
PZL
t
PZH
Output Enable Time
ˉˉ
A
to OA
n
, ˉˉ
Output Disable Time
ˉˉ
A
to OA
n
, ˉˉ
B
to OB
n
-
5.2
nS
t
PLZ
t
PHZ
B
to OB
n
-
5.2
nS
f
MAX
Input Frequency
C
L
= 15pF
f
≤
133MHz
-
133
MHz
t
PLH
t
PHL
Propagation Delay
IN
A
to OA
n
, INB to OB
n
0.5
2.5
nS
t
R
Output Rise Time
(Measured from 0.7V to 1.7V)
-
1.25
nS
t
F
Output Fall Time
(Measured from 1.7V to 0.7V)
-
1.25
nS
t
SK(O)
Same device output pin to pin skew
5
-
200
pS
t
SK(P)
Pulse skew
6,9
-
270
pS
t
SK(PP)
Part to part skew
7
-
550
pS
t
PZL
t
PZH
Output Enable Time
ˉˉ
A
to OA
n
, ˉˉ
Output Disable Time
ˉˉ
A
to OA
n
, ˉˉ
B
to OB
n
-
5.2
nS
t
PLZ
t
PHZ
B
to OB
n
-
5.2
nS
f
MAX
Input Frequency
C
L
= 15pF
133MHz
≤
f
≤
166MHz
-
166
MHz
Notes:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. t
and t
are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to V
CC
, operating temperature and process parameters. These propagation delay limits do not
imply skew.
5. Skew measured between all outputs under identical transitions and load conditions.
6. Skew measured is difference between propagation delay times t
PHL
and t
PLH
of same outputs under identical load conditions.
7. Part to part skew for all outputs given identical transitions and load conditions at identical V
CC
levels and temperature.
8. Airflow of 1m/s is recommended for frequencies above 133MHz.
9. This parameter is measured using f = 1MHz.
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| ASM2P20805A-20-AT | 2.5V CMOS Dual 1-To-5 Clock Driver |
| ASM2P20805A-20-DR | 2.5V CMOS Dual 1-To-5 Clock Driver |
| ASM2P20805A-20-DT | GS-GSK |
| ASM2P20805A | 2.5V CMOS Dual 1-To-5 Clock Driver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM2P20805A-20-AT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V CMOS Dual 1-To-5 Clock Driver |
| ASM2P20805A-20-DR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V CMOS Dual 1-To-5 Clock Driver |
| ASM2P20805A-20-DT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V CMOS Dual 1-To-5 Clock Driver |
| ASM2P20807A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V CMOS 1-TO-10 CLOCK DRIVER |
| ASM2P20807A-20-AR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V CMOS 1-TO-10 CLOCK DRIVER |
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