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參數(shù)資料
| 型號(hào)： | ASM2I99448-32-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| 中文描述： | 99448 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁(yè)數(shù)： | 7/15頁(yè) |
| 文件大?。?/td> | 594K |
| 代理商： | ASM2I99448-32-ET |
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May 2005
rev 0.3
ASM2I99448
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
7 of
15
APPLICATIONS INFORMATION
Timing Diagram
Figure 1. Output Clock Stop (CLK_STOP)
Driving Transmission Lines
The ASM2I99448 clock driver was designed to drive high
speed signals in a terminated transmission line
environment. To provide the optimum flexibility to the
user, the output drivers were designed to exhibit the
lowest impedance possible. With an output impedance of
17
(V
CC
=3.3V), the outputs can drive either parallel or
series terminated transmission lines. In most high
performance clock networks, point–to–point distribution of
signals is the method of choice. In a point–to–point
scheme, either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a 50
resistance to V
CC
÷2.
ASM2I99448
OUTPUT BUFFER
Figure 2. Single versus Dual Transmission
Lines
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the ASM2I99448 clock driver. For the series
terminated case, however, there is no DC current draw;
thus, the outputs can drive multiple series terminated
lines. Figure 2 “Single versus Dual Transmission Lines”
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken
to its extreme, the fanout of the ASM2I99448 clock driver
is effectively doubled due to its capability to drive multiple
lines at V
CC
=3.3V.
The waveform plots in Figure 3 “Single versus Dual Line
Termination Waveforms” show the simulation results of
an output driving a single line versus two lines. In both
Figure 3 . Single versus Dual Line Termination
Waveforms
cases, the drive capability of the ASM2I99448 output
buffer is more than sufficient to drive 50
transmission
lines on the incident edge. Note from the delay
measurements in the simulations a delta of only 43pS
exists between the two differently loaded outputs. This
suggests that the dual line driving need not be used
exclusively to maintain the tight output–to–output skew of
the ASM2I99448. The output waveform in Figure 3
“Single versus Dual Line Termination Waveforms” shows
a step in the waveform; this step is caused by the
impedance mismatch seen looking into the driver. The
parallel combination of the 33
series resistor plus the
output impedance does
combination of the line impedances. The voltage wave
launched down the two lines will equal:
V
L
= V
S
( Z0
÷ (R
S
+R
0
+Z
0
))
Z
0
= 50
|| 50
R
S
= 33
|| 33
R
0
= 17
V
L
= 3.0 ( 25 ÷ (16.5+17+25)
= 1.28V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.5V. It will then increment
towards the quiescent 3.0V in steps separated by one
round trip delay (in this case 4.0nS).
Since this step is well above the threshold region it will
not cause any false clock triggering; however, designers
may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving
not match the parallel
17
Z
0
=50
R
S
=33
ASM2I99448
OUTPUT BUFFER
17
Z
0
=50
R
S
=33
Z
0
=50
R
S
=33
CCLK or
PCLK
CLK _ STOP
Q0 to Q11
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
TIME (nS)
V
In
OutA
t
D
= 3.8956
OutB
t
D
= 3.9386
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM2I99448-32-LR | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448-32-LT | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99456G-32-ER | 3.3V/2.5V LVCMOS Clock Fanout Buffer |
| ASM2I99456G-32-ET | 3.3V/2.5V LVCMOS Clock Fanout Buffer |
| ASM2I99456G-32-LR | 3.3V/2.5V LVCMOS Clock Fanout Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM2I99448-32-LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448G-32-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448G-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448G-32-LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
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