參數(shù)資料
型號(hào): ASM2I9940LG-32-LT
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: 時(shí)鐘及定時(shí)
英文描述: Low Voltage 1:18 Clock Distribution Chip
中文描述: 9940 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, GREEN, LQFP-32
文件頁(yè)數(shù): 6/13頁(yè)
文件大?。?/td> 223K
代理商: ASM2I9940LG-32-LT
June 2005
rev 1.0
ASM2I9940L
Low Voltage 1:18 Clock Distribution Chip
6 of
13
Notice: The information in this document is subject to change without notice.
Table 9. DC Characteristics
(T
A
= 0° to 70°C, V
CCI
= 2.5V ± 5%, V
CCO
= 2.5V ± 5%)
Symbol
V
IH
V
IL
Characteristic
Min
2.4
Typ
Max
V
CCI
0.8
Unit
V
V
Condition
Input HIGH Voltage
Input LOW Voltage
Peak–to–Peak Input
Voltage
Common Mode Range
Output HIGH Voltage
Output LOW Voltage
Input Current
Input Capacitance
Power Dissipation Capacitance
Output Impedance
Maximum Quiescent Supply Current
CMOS_CLK
CMOS_CLK
V
PP
PECL_CLK
500
1000
mV
V
CMR
V
OH
V
OL
I
IN
C
IN
C
pd
Z
OUT
I
CC
PECL_CLK
V
CC
–1.0
1.8
18
V
CC
–0.6
0.5
±200
28
1.0
V
V
V
μA
pF
pF
mA
I
OH
= –20mA
I
OH
= 20mA
per output
4.0
10
23
0.5
Table 10. AC Characteristics
(T
A
= 0° to 70°C, V
CCI
= 2.5V ± 5%, V
CCO
= 2.5V ± 5%)
Symbol
F
max
Characteristic
Min
Typ
2.6
2.3
2.8
2.3
Max
200
5.2
4.0
5.0
4.0
Unit
MHz
Condition
Maximum Input Frequency
t
PLH
Propagation Delay
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
4.0
3.1
3.8
3.1
nS
Note
1
.
t
PLH
Propagation Delay
nS
t
sk(o)
Output-to-output Skew
Within one bank
PECL_CLK
CMOS_CLK
200
200
pS
Note
1
.
t
sk(pp)
Part–to–Part Skew
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
PECL_CLK
CMOS_CLK
f
CLK
< 134 MHz
f
CLK
<250 MHz
2.6
1.7
2.2
1.7
1.2
1.0
55
60
1.2
nS
Notes
1,2
t
sk(pp)
Part–to–Part Skew
nS
Notes
1,2
t
sk(pp)
Part–to–Part Skew
nS
Notes
1,3
DC
Output Duty Cycle
45
40
0.3
50
50
%
%
nS
Input DC = 50%
Input DC = 50%
0.5 – 1.8 V
t
r
, t
f
Output Rise/Fall Time
Note: 1. Tested using standard input levels, Production tested @ 150MHz.
2. Across temperature and voltage ranges, includes output skew.
3. For a specific temperature and voltage, includes output skew.
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