參數(shù)資料
型號(hào): ASM2I9940L
廠商: Alliance Semiconductor Corporation
英文描述: Low Voltage 1:18 Clock Distribution Chip
中文描述: 低壓1:18時(shí)鐘分配芯片
文件頁(yè)數(shù): 7/13頁(yè)
文件大小: 223K
代理商: ASM2I9940L
June 2005
rev 1.0
ASM2I9940L
Low Voltage 1:18 Clock Distribution Chip
7 of
13
Notice: The information in this document is subject to change without notice.
Figure 1. LVCMOS_CLK ASM2I9940L AC Test Reference for V
CC
= 3.3V and V
CC
= 2.5V
V
TT
V
TT
Figure 2. PECL_CLK ASM2I9940L AC Test Reference for V
CC
= 3.3V and V
CC
= 2.5V
V
CC
÷2
GND
Figure 3. Propagation Delay (t
PD
) Test Reference
PECL_CLK
Q
V
PP
V
CMR
V
CC
t
PD
PECL_CLK
V
CC
÷2
GND
V
C
V
CC
÷2
GND
LVCMOS_CLK
Q
V
C
t
PD
Figure 4. LVCMOS Propagation Delay (t
PD
) Test Reference
The time from the PLL controlled edge to the
non-controlled edge, divided by the time
between PLL controlled edges, expressed as a
percentage.
Figure 5. Output Duty Cycle (DC)
V
CC
V
CC
÷2
GND
DC (t
P
÷T
0
Χ
100%)
t
P
T
0
t
SK(O)
V
OH
V
CC
÷2
GND
V
CC
V
CC
÷2
GND
The pin-to-pin skew is defined as the worst case
difference in propagation delay between any similar
delay path within a single device
Figure 6. Output–to–Output Skew t
SK(O)
t
R
V
CC
= 3.3V V
CC
= 2.5V
2.4
0.55 0.6V
1.8V
t
F
Figure 7. Output Transition Time Test Reference
t
R
V
CC
= 3.3V V
CC
= 2.5V
2.0 1.7V
0.8 0.7V
t
F
Figure 8. Input Transition Time Test Reference
Pulse
Generator
Z=50
Z
0
=50
Z
0
=50
R
T
=50
R
T
=50
V
TT
ASM2I9940L
Differential
Pulse Generator
Z=50
Z
0
=50
Z
0
=50
R
T
= 50
V
TT
R
T
=50
ASM2I9940L
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