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參數(shù)資料
| 型號(hào)： | ASM2I2318ANZ-48-AT |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Circular Connector; No. of Contacts:61; Series:MS27508; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:24; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:24-61 RoHS Compliant: No |
| 中文描述： | 2318 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 547K |
| 代理商： | ASM2I2318ANZ-48-AT |
June 2005
rev 0.3
ASM2I2318ANZ
18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
3 of
13
Notice: The information in this document is subject to change without notice.
Device Functionality
OE
0
SDRAM [0-17]
Hi-Z
1
1 x BUF_IN
Serial Configuration Map
The Serial bits will be read by the clock driver in the
following order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Reserved bits should be programmed to “0” or ”1”.
Serial interface address for the ASM2I2318ANZ is:
A6
A5
A4
A3
1
1
0
1
A2
0
A1
0
A0
1
R/W
----
Byte 0:SDRAM Active/Inactive Register
(1 = Enable, 0 = Disable), Default = Enable
Bit
Pin #
Description
Bit 7
18
SDRAM7 (Active/Inactive)
Bit 6
17
SDRAM6 (Active/Inactive)
Bit 5
14
SDRAM5 (Active/Inactive)
Bit 4
13
SDRAM4 (Active/Inactive)
Bit 3
9
SDRAM3 (Active/Inactive)
Bit 2
8
SDRAM2 (Active/Inactive)
Bit 1
5
SDRAM1 (Active/Inactive)
Bit 0
4
SDRAM0 (Active/Inactive)
Byte 1: SDRAM Active/Inactive Register
(1 = Enable, 0 = Disable), Default = Enable
Bit
Pin #
Description
Bit 7
45
SDRAM15 (Active/Inactive)
Bit 6
44
SDRAM14 (Active/Inactive)
Bit 5
41
SDRAM13 (Active/Inactive)
Bit 4
40
SDRAM12 (Active/Inactive)
Bit 3
36
SDRAM11 (Active/Inactive)
Bit 2
35
SDRAM10 (Active/Inactive)
Bit 1
32
SDRAM9 (Active/Inactive)
Bit 0
31
SDRAM8 (Active/Inactive)
Byte 2: SDRAM Active/Inactive Register
(1 = Enable, 0 = Disable), Default = Enable
Bit
Pin #
Description
Bit 7
28
SDRAM17 (Active/Inactive)
Bit 6
21
SDRAM16 (Active/Inactive)
Bit 5
--
Reserved
Bit 4
--
Reserved
Bit 3
--
Reserved
Bit 2
--
Reserved
Bit 1
--
Reserved
Bit 0
--
Reserved
Note 1 : When the value of bit in these bytes is high, the output is enabled. When the value of the bit is low, the output is forced to low state. The default value
of all the bits is high after chip is powered up.
IIC Byte Flow
Byte
Description
1
IIC Address
2
Command (dummy value, ignored)
3
Byte Count (dummy value, ignored)
4
IIC Data Byte 0
5
IIC Data Byte 1
6
IIC Data Byte 2
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