參數(shù)資料
型號: ASM1810-10/S
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PBCY3
封裝: TO-92, 3 PIN
文件頁數(shù): 3/8頁
文件大?。?/td> 243K
代理商: ASM1810-10/S
3 of 8
Notice: The information in this document is subject to change without notice
Low Power, 5V P Reset
ASM1810
October 2003
rev 1.0
Application Information
Operation - Power Monitor
The
ASM1810
detects
out-of-tolerance
power
supply
conditions. It resets a processor during power-up, power-down
and issues a reset to the system processor when the monitored
power supply voltage is below the reset threshold. When an
out-of-tolerance VCC voltage is detected, the RESET signal is
asserted. On power-up, RESET is kept active (LOW) for
approximately 150ms after the power supply voltage has
reached the selected tolerance. This allows the power supply
and microprocessor to stabilize before RESET is released.
Output Conditions
The ASM1810 active LOW reset signal is valid as long as VCC
remains below 1.2V. The RESET output on the ASM1810 uses
a push-pull drive stage that can maintain a valid output below
1.2V. To sink current with VCC below 1.2V, a resistor can be
connected from the reset pin (RESET) to Ground (see Figure
1). This configuration will give a valid value on the RESET
output with VCC approaching 0V. During both power up and
down, this configuration will draw current when the RESET is in
the high state. A value of 100k
should be adequate to
maintain a valid connection.
Microprocessor
RESET
ASM1810
100k
Figure 1: RESET Valid to 0V VCC
~
VOH
RESET
~
tRPU
VCCTP (MIN)
VCCTP
VCCTP (MAX)
tR
VCC
~
Figure 2: Timing Diagram: Power-Up
~ ~
VCCTP (MIN)
VCCTP
VCCTP (MAX)
tF
VCC
tRPD
VOL
RESET
Figure 3: Timing Diagram: Power-Down
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