參數(shù)資料
型號: ASM1232LPSNF
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: 5V uP Power Supply Monitor and Reset Circuit
中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
封裝: LEAD FREE, SOIC-8
文件頁數(shù): 6/10頁
文件大?。?/td> 276K
代理商: ASM1232LPSNF
ASM1232LP/LPS
6 of 10
Notice: The information in this document is subject to change without notice
5V μP Power Supply Monitor and Reset Circuit
January 2005
rev 1.5
Notes
1. PBRST is internally pulled HIGH to V
CC
through a nominal 40k
resistor.
2. RESET is an open drain output.
3. RESET remains within 0.5V of V
CC
on power-down until V
CC
falls below 2V. RESET remains within 0.5V of ground on power-down until V
CC
falls below 2.0V.
4. Must not exceed the minimum watchdog time-out period (t
TD
). The watchdogcircuit cannot be disabled. To avoid a reset, ST must be strobed.
Input Leakage
I
IL
Note 1
-1.0
1.0
μA
RESET Low Level
V
OL
Note 3
0.4
V
Internal Pull-up Resistor
Note 1
40
k
Operating Current (CMOS)
I
CC1
30
μA
Input Capacitance
C
IN
5
pF
Output Capacitance
C
OUT
10
pF
PBRST Manual Reset
Minimum Low Time
t
PB
PBRST = V
IL
20
ms
Reset Active Time
t
RST
250
610
1000
ms
ST Pulse Width
t
ST
Note 4
20
ns
V
CC
Fail Detect to RESET or
RESET
t
RPD
5
8
μs
V
CC
Slew Rate
t
F
4.75V to 4.25V
300
μs
PBRST Stable LOW to RESET and
RESET Active
t
PDLY
20
ms
V
CC
Detect to RESET or RESET
inactive
t
RPU
t
RISE
= 5μs
250
610
1000
ms
V
CC
Slew Rate
t
R
4.25V to 4.75V
0
ns
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
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