參數(shù)資料
型號： AS9C25512M2018L-166TI
廠商： ALLIANCE SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： TERM. F/O CABLE ST-SC/ DPLX/RISER/10M/ORANGE
中文描述： 512K X 18 DUAL-PORT SRAM, 10 ns, PQFP144
封裝： TQFP-144
文件頁數(shù)： 21/30頁
文件大?。?/td> 1100K
代理商： AS9C25512M2018L-166TI
AS9C25512M2018L
AS9C25256M2018L
9/24/04, v.1.2
Alliance Semiconductor
P. 21 of 30
Snooze mode
Snooze mode is a low-current, power-down mode in which the corresponding port is deselected and its current is reduced to a
very low value. Both ports are equipped with independent SNOOZE inputs (ZZ). During Snooze mode, all inputs of the port
except ZZ are internally disabled and all its Outputs go to High-Z.
ZZ is an asynchronous, active HIGH input that causes the selected port to enter Snooze mode. If both ports go into Snooze mode,
the device is deselected and current is reduced to I
ZZ
. When ZZ
A
and ZZ
B
become a logic HIGH, I
ZZ
is guaranteed after the
setup time t
SCZZ
is met.
Any READ or WRITE operation pending when the port enters Snooze mode is not guaranteed to complete. Therefore, Snooze
mode must not be initiated until valid pending operations are completed. Similarly during the time t
RCZZ
, when the port is
transitioning out of snooze mode, only DESELECT cycles should be given.
Snooze mode electrical characteristics
Description
SNOOZE MODE Current
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to enter Snooze Current
ZZ inactive to exit Snooze Current
Snooze mode timing waveform
[1,3]
Notes:
1. During Snooze mode, all dynamic inputs are disabled (except JTAG inputs). During JTAG operations, ZZ
x
must be held Low in order to capture the parallel inputs of the bound-
ary scan register. All static inputs (i.e. PL/FT
x
,OPT
x
) and ZZ
x
themselves are not affected during snooze mode.
2. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H).
3. All timings are same for Port A and Port B.
4. Minimum of two deselect cycles should be given before asserting snooze and minimum of two deselect cycles should be given after de-asserting snooze to guarantee data
integrity.
5. Select cycles indicated before and after Snooze are Read cycles. They can also be Write cycles.
Conditions
ZZ
A
= ZZ
B
>= V
IH
Symbol
I
ZZ
t
SCZZ
t
RCZZ
t
SIZZ
t
RIZZ
Min
15
-
2
-
0
Max
18
2
-
2
-
Units
mA
cycle
cycle
cycle
cycle
CLK
t
CH
t
CYC
t
CL
Don’t care
t
CEH
t
CES
t
SIZZ
t
RIZZ
IZZ
t
SCZZ
ZZ setup cycles
t
RCZZ
ZZ recovery cycles
High-Z
CE
[2,4]
ZZ
I
Supply
OUTPUTS
[5]
(Qout)
INPUTS
(Except ZZ)
t
HZC
t
LZC
Undefined
Valid
Valid
相關PDF資料
PDF描述
AS9C25256M2018L-166TI TERM. F/O CABLE SC-SC/ DPLX/RISER/1M/BLUE
AS9C25512M2018L-200BC TERM. F/O CABLE SC-SC/ DPLX/RISER/2M/BLUE
AS9C25256M2018L-200BC TERM. F/O CABLE SC-SC/ DPLX/RISER/3M/BLUE
AS9C25512M2018L-200BI TERM. F/O CABLE SC-SC/ DPLX/RISER/5M/BLUE
AS9C25256M2018L-200BI TERM. F/O CABLE SC-SC/ DPLX/RISER/10M/BLUE
相關代理商/技術參數(shù)
參數(shù)描述
AS9C25512M2018L-200BC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25512M2018L-200BI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25512M2018L-200FC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25512M2018L-200FI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25512M2018L-200TC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
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